-- -- Copyright (C) 1988-2000 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. -- CHIP vmefpga2 BEGIN |EN_3V_PU : OUTPUT_PIN = 180; |mux_r_bsy : INPUT_PIN = 78; |DATA_SEL : OUTPUT_PIN = 207; |M_/CLR : OUTPUT_PIN = 208; |CLK_SEL : OUTPUT_PIN = 104; |V_CONTROL : OUTPUT_PIN = 111; |busy : INPUT_PIN = 184; |pu_irq1 : INPUT_PIN = 205; |pu_irq2 : INPUT_PIN = 206; |ttc_dat7 : OUTPUT_PIN = 203; |ttc_dat6 : OUTPUT_PIN = 202; |ttc_dat5 : OUTPUT_PIN = 200; |ttc_dat4 : OUTPUT_PIN = 199; |ttc_dat3 : OUTPUT_PIN = 198; |ttc_dat2 : OUTPUT_PIN = 197; |ttc_dat1 : OUTPUT_PIN = 196; |ttc_type : OUTPUT_PIN = 193; |ttc_bcid : OUTPUT_PIN = 192; |ttc_rstn : OUTPUT_PIN = 204; |fifo_/oe : OUTPUT_PIN = 29; |feb_linkrst : OUTPUT_PIN = 28; |feb_linkst : OUTPUT_PIN = 27; |feb_do14 : OUTPUT_PIN = 25; |feb_do13 : OUTPUT_PIN = 24; |feb_do12 : OUTPUT_PIN = 19; |feb_do11 : OUTPUT_PIN = 18; |feb_do10 : OUTPUT_PIN = 17; |feb_do9 : OUTPUT_PIN = 16; |feb_do8 : OUTPUT_PIN = 15; |feb_do7 : OUTPUT_PIN = 14; |feb_do6 : OUTPUT_PIN = 13; |feb_do5 : OUTPUT_PIN = 12; |feb_do4 : OUTPUT_PIN = 11; |feb_do3 : OUTPUT_PIN = 10; |feb_do2 : OUTPUT_PIN = 9; |feb_do1 : OUTPUT_PIN = 8; |feb_do0 : OUTPUT_PIN = 7; |FEB_DO15 : OUTPUT_PIN = 26; |TTC_DAT0 : OUTPUT_PIN = 195; |V_DAT0 : BIDIR_PIN = 191; |V_DAT8 : BIDIR_PIN = 190; |V_DAT1 : BIDIR_PIN = 189; |V_DAT9 : BIDIR_PIN = 187; |V_DAT2 : BIDIR_PIN = 186; |V_DAT10 : BIDIR_PIN = 179; |V_DAT3 : BIDIR_PIN = 177; |V_DAT11 : BIDIR_PIN = 176; |V_DAT4 : BIDIR_PIN = 175; |V_DAT12 : BIDIR_PIN = 174; |V_DAT5 : BIDIR_PIN = 173; |V_DAT13 : BIDIR_PIN = 172; |V_DAT6 : BIDIR_PIN = 170; |V_DAT7 : BIDIR_PIN = 168; |V_DAT14 : BIDIR_PIN = 169; |V_DAT15 : BIDIR_PIN = 167; |T1_/OE : OUTPUT_PIN = 164; |V_WORD : INPUT_PIN = 163; |V_/WRITE : INPUT_PIN = 162; |V_A17 : INPUT_PIN = 161; |V_A16 : INPUT_PIN = 160; |V_A15 : INPUT_PIN = 159; |V_A14 : INPUT_PIN = 158; |V_A13 : INPUT_PIN = 157; |V_/SYSRST : INPUT_PIN = 182; |V_A12 : INPUT_PIN = 150; |V_A11 : INPUT_PIN = 149; |V_A10 : INPUT_PIN = 148; |V_A9 : INPUT_PIN = 147; |V_A8 : INPUT_PIN = 144; |V_A7 : INPUT_PIN = 143; |V_A6 : INPUT_PIN = 142; |V_/DS : INPUT_PIN = 141; |DTACK_V : OUTPUT_PIN = 140; |DIR_2 : OUTPUT_PIN = 139; |V_DAT16 : BIDIR_PIN = 136; |V_DAT17 : BIDIR_PIN = 135; |V_DAT18 : BIDIR_PIN = 134; |V_DAT19 : BIDIR_PIN = 133; |V_DAT20 : BIDIR_PIN = 132; |V_DAT21 : BIDIR_PIN = 131; |V_DAT22 : BIDIR_PIN = 128; |V_DAT23 : BIDIR_PIN = 127; |V_DAT24 : BIDIR_PIN = 126; |V_DAT25 : BIDIR_PIN = 125; |V_DAT26 : BIDIR_PIN = 122; |V_DAT27 : BIDIR_PIN = 121; |V_DAT28 : BIDIR_PIN = 120; |V_DAT29 : BIDIR_PIN = 119; |V_DAT30 : BIDIR_PIN = 116; |V_DAT31 : BIDIR_PIN = 115; |T2_/OE : OUTPUT_PIN = 114; |PU_DSN : BIDIR_PIN = 113; |PU_R/W : OUTPUT_PIN = 112; |PU_D0 : BIDIR_PIN = 103; |PU_D2 : BIDIR_PIN = 102; |PU_D1 : BIDIR_PIN = 101; |PU_D3 : BIDIR_PIN = 99; |PU_D4 : BIDIR_PIN = 100; |PU_D5 : BIDIR_PIN = 97; |PU_D6 : BIDIR_PIN = 96; |PU_RDY : INPUT_PIN = 95; |PU_D7 : BIDIR_PIN = 94; |PU_/RST : OUTPUT_PIN = 93; |PU_/CS : OUTPUT_PIN = 92; |PU_ADD0 : OUTPUT_PIN = 90; |PU_ADD1 : OUTPUT_PIN = 89; |PU_ADD2 : OUTPUT_PIN = 88; |PU_ADD3 : OUTPUT_PIN = 87; |FIFO_EVTEND : OUTPUT_PIN = 86; |FIFO_/REN : OUTPUT_PIN = 85; |FIFO_EVTRDY : INPUT_PIN = 83; |FIFO_DI31 : INPUT_PIN = 75; |FIFO_DI30 : INPUT_PIN = 74; |FIFO_DI29 : INPUT_PIN = 73; |FIFO_DI28 : INPUT_PIN = 71; |FIFO_DI27 : INPUT_PIN = 70; |FIFO_DI26 : INPUT_PIN = 69; |FIFO_DI25 : INPUT_PIN = 68; |FIFO_DI24 : INPUT_PIN = 67; |FIFO_DI23 : INPUT_PIN = 65; |FIFO_DI22 : INPUT_PIN = 64; |FIFO_DI21 : INPUT_PIN = 63; |FIFO_DI20 : INPUT_PIN = 62; |FIFO_DI19 : INPUT_PIN = 61; |FIFO_DI18 : INPUT_PIN = 60; |FIFO_DI17 : INPUT_PIN = 58; |FIFO_DI16 : INPUT_PIN = 57; |FIFO_DI15 : INPUT_PIN = 56; |FIFO_DI14 : INPUT_PIN = 55; |FIFO_DI13 : INPUT_PIN = 54; |FIFO_DI12 : INPUT_PIN = 53; |FIFO_DI11 : INPUT_PIN = 47; |FIFO_DI10 : INPUT_PIN = 46; |FIFO_DI9 : INPUT_PIN = 45; |FIFO_DI8 : INPUT_PIN = 44; |FIFO_DI7 : INPUT_PIN = 41; |FIFO_DI6 : INPUT_PIN = 40; |FIFO_DI5 : INPUT_PIN = 39; |FIFO_DI4 : INPUT_PIN = 38; |FIFO_DI3 : INPUT_PIN = 37; |FIFO_DI2 : INPUT_PIN = 36; |FIFO_DI1 : INPUT_PIN = 31; |FIFO_DI0 : INPUT_PIN = 30; |dir_1 : OUTPUT_PIN = 166; |CLK : INPUT_PIN = 79; DEVICE = EPF10K30EQC208-2; END; DEFAULT_DEVICES BEGIN AUTO_DEVICE = EPF10K200SFC672-1X; AUTO_DEVICE = EPF10K200SFC672-1; AUTO_DEVICE = EPF10K200SBC600-1X; AUTO_DEVICE = EPF10K200SBC600-1; AUTO_DEVICE = EPF10K200SFC484-1X; AUTO_DEVICE = EPF10K200SFC484-1; AUTO_DEVICE = EPF10K200SBC356-1X; AUTO_DEVICE = EPF10K200SBC356-1; AUTO_DEVICE = EPF10K200SRC240-1X; AUTO_DEVICE = EPF10K200SRC240-1; AUTO_DEVICE = EPF10K200EFC672-1; AUTO_DEVICE = EPF10K200EBC600-1; AUTO_DEVICE = EPF10K200EGC599-1; AUTO_DEVICE = EPF10K130EFC672-1X; AUTO_DEVICE = EPF10K130EFC672-1; AUTO_DEVICE = EPF10K130EBC600-1X; AUTO_DEVICE = EPF10K130EBC600-1; AUTO_DEVICE = EPF10K130EFC484-1X; AUTO_DEVICE = EPF10K130EFC484-1; AUTO_DEVICE = EPF10K130EBC356-1X; AUTO_DEVICE = EPF10K130EBC356-1; AUTO_DEVICE = EPF10K130EQC240-1X; AUTO_DEVICE = EPF10K130EQC240-1; AUTO_DEVICE = EPF10K100EFC484-1X; AUTO_DEVICE = EPF10K100EFC484-1; AUTO_DEVICE = EPF10K100EBC356-1X; AUTO_DEVICE = EPF10K100EBC356-1; AUTO_DEVICE = EPF10K100EFC256-1X; AUTO_DEVICE = EPF10K100EFC256-1; AUTO_DEVICE = EPF10K100EQC240-1X; AUTO_DEVICE = EPF10K100EQC240-1; AUTO_DEVICE = EPF10K100EQC208-1X; AUTO_DEVICE = EPF10K100EQC208-1; AUTO_DEVICE = EPF10K50SFC484-1X; AUTO_DEVICE = EPF10K50SFC484-1; AUTO_DEVICE = EPF10K50SBC356-1X; AUTO_DEVICE = EPF10K50SBC356-1; AUTO_DEVICE = EPF10K50SFC256-1X; AUTO_DEVICE = EPF10K50SFC256-1; AUTO_DEVICE = EPF10K50SQC240-1X; AUTO_DEVICE = EPF10K50SQC240-1; AUTO_DEVICE = EPF10K50SQC208-1X; AUTO_DEVICE = EPF10K50SQC208-1; AUTO_DEVICE = EPF10K50STC144-1X; AUTO_DEVICE = EPF10K50STC144-1; AUTO_DEVICE = EPF10K50EFC484-1; AUTO_DEVICE = EPF10K50EFC256-1; AUTO_DEVICE = EPF10K50EQC240-1; AUTO_DEVICE = EPF10K50EQC208-1; AUTO_DEVICE = EPF10K50ETC144-1; AUTO_DEVICE = EPF10K30EFC484-1X; AUTO_DEVICE = EPF10K30EFC484-1; AUTO_DEVICE = EPF10K30EFC256-1X; AUTO_DEVICE = EPF10K30EFC256-1; AUTO_DEVICE = EPF10K30EQC208-1X; AUTO_DEVICE = EPF10K30EQC208-1; AUTO_DEVICE = EPF10K30ETC144-1X; AUTO_DEVICE = EPF10K30ETC144-1; ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; END; TIMING_POINT BEGIN FREQUENCY = 49mhz; DEVICE_FOR_TIMING_SYNTHESIS = EPF10K30EQC208-2; CUT_ALL_BIDIR = ON; CUT_ALL_CLEAR_PRESET = ON; MAINTAIN_STABLE_SYNTHESIS = OFF; END; IGNORED_ASSIGNMENTS BEGIN IGNORE_CLIQUE_ASSIGNMENTS = OFF; IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; IGNORE_TIMING_ASSIGNMENTS = OFF; IGNORE_CHIP_ASSIGNMENTS = OFF; IGNORE_PIN_ASSIGNMENTS = OFF; IGNORE_LC_ASSIGNMENTS = OFF; IGNORE_DEVICE_ASSIGNMENTS = OFF; IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; FIT_IGNORE_TIMING = ON; END; GLOBAL_PROJECT_DEVICE_OPTIONS BEGIN FLEX_CONFIGURATION_EPROM = EPC1PC8; RESERVED_LCELLS_PERCENT = 0; RESERVED_PINS_PERCENT = 0; SECURITY_BIT = OFF; USER_CLOCK = OFF; AUTO_RESTART = OFF; RELEASE_CLEARS = OFF; ENABLE_DCLK_OUTPUT = OFF; DISABLE_TIME_OUT = OFF; CONFIG_SCHEME = ACTIVE_SERIAL; FLEX8000_ENABLE_JTAG = OFF; DATA0 = RESERVED_TRI_STATED; DATA1_TO_DATA7 = UNRESERVED; nWS_nRS_nCS_CS = UNRESERVED; RDYnBUSY = UNRESERVED; RDCLK = UNRESERVED; SDOUT = RESERVED_DRIVES_OUT; ADD0_TO_ADD12 = UNRESERVED; ADD13 = UNRESERVED; ADD14 = UNRESERVED; ADD15 = UNRESERVED; ADD16 = UNRESERVED; ADD17 = UNRESERVED; CLKUSR = UNRESERVED; nCEO = UNRESERVED; ENABLE_CHIP_WIDE_RESET = OFF; ENABLE_CHIP_WIDE_OE = OFF; ENABLE_INIT_DONE_OUTPUT = OFF; FLEX10K_JTAG_USER_CODE = 7F; CONFIG_SCHEME_10K = PASSIVE_SERIAL; MAX7000S_USER_CODE = FFFF; FLEX10K_ENABLE_LOCK_OUTPUT = OFF; MAX7000S_ENABLE_JTAG = ON; MULTIVOLT_IO = OFF; CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; FLEX6000_ENABLE_JTAG = OFF; FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; MAX7000AE_USER_CODE = FFFFFFFF; MAX7000AE_ENABLE_JTAG = ON; CONFIG_EPROM_USER_CODE = FFFFFFFF; CONFIG_EPROM_PULLUP_RESISTOR = ON; MAX7000B_VCCIO_IOBANK1 = 3.3V; MAX7000B_VCCIO_IOBANK2 = 3.3V; MAX7000B_ENABLE_VREFA = OFF; MAX7000B_ENABLE_VREFB = OFF; END; GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS BEGIN OPTIMIZE_FOR_SPEED = 8; MULTI_LEVEL_SYNTHESIS_MAX9000 = OFF; STYLE = FAST; AUTO_FAST_IO = ON; DEVICE_FAMILY = FLEX10KE; MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; AUTO_GLOBAL_CLOCK = ON; AUTO_GLOBAL_CLEAR = ON; AUTO_GLOBAL_PRESET = ON; AUTO_GLOBAL_OE = ON; AUTO_REGISTER_PACKING = OFF; ONE_HOT_STATE_MACHINE_ENCODING = OFF; AUTO_OPEN_DRAIN_PINS = ON; AUTO_IMPLEMENT_IN_EAB = OFF; END; COMPILER_PROCESSING_CONFIGURATION BEGIN DESIGN_DOCTOR = OFF; DESIGN_DOCTOR_RULES = EPLD; FUNCTIONAL_SNF_EXTRACTOR = OFF; TIMING_SNF_EXTRACTOR = ON; OPTIMIZE_TIMING_SNF = OFF; LINKED_SNF_EXTRACTOR = OFF; RPT_FILE_EQUATIONS = ON; RPT_FILE_HIERARCHY = ON; RPT_FILE_LCELL_INTERCONNECT = ON; RPT_FILE_USER_ASSIGNMENTS = ON; GENERATE_AHDL_TDO_FILE = OFF; SMART_RECOMPILE = OFF; FITTER_SETTINGS = NORMAL; PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; END; COMPILER_INTERFACES_CONFIGURATION BEGIN NETLIST_OUTPUT_TIME_SCALE = 0.1ns; EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; EDIF_BUS_DELIMITERS = []; EDIF_FLATTEN_BUS = OFF; EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; EDIF_OUTPUT_USE_EDC = OFF; EDIF_INPUT_USE_LMF2 = OFF; EDIF_INPUT_USE_LMF1 = OFF; EDIF_OUTPUT_GND = GND; EDIF_OUTPUT_VCC = VCC; EDIF_INPUT_GND = GND; EDIF_INPUT_VCC = VCC; EDIF_OUTPUT_EDC_FILE = *.edc; EDIF_INPUT_LMF2 = *.lmf; EDIF_INPUT_LMF1 = *.lmf; VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; VHDL_FLATTEN_BUS = OFF; VERILOG_FLATTEN_BUS = OFF; EDIF_TRUNCATE_HIERARCHY_PATH = OFF; VHDL_TRUNCATE_HIERARCHY_PATH = OFF; VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; EDIF_NETLIST_WRITER = OFF; EDIF_OUTPUT_VERSION = 200; XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; XNF_GENERATE_AHDL_TDX_FILE = ON; VERILOG_NETLIST_WRITER = OFF; VHDL_NETLIST_WRITER = OFF; USE_SYNOPSYS_SYNTHESIS = OFF; SYNOPSYS_COMPILER = DESIGN; SYNOPSYS_DESIGNWARE = OFF; SYNOPSYS_HIERARCHICAL_COMPILATION = ON; SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; SYNOPSYS_MAPPING_EFFORT = MEDIUM; VHDL_READER_VERSION = VHDL87; VHDL_WRITER_VERSION = VHDL87; END; CUSTOM_DESIGN_DOCTOR_RULES BEGIN RIPPLE_CLOCKS = ON; GATED_CLOCKS = ON; MULTI_LEVEL_CLOCKS = ON; MULTI_CLOCK_NETWORKS = ON; STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; PRESET_CLEAR_NETWORKS = ON; ASYNCHRONOUS_INPUTS = ON; DELAY_CHAINS = ON; RACE_CONDITIONS = ON; EXPANDER_NETWORKS = ON; MASTER_RESET = OFF; END; SIMULATOR_CONFIGURATION BEGIN END_TIME = 3.0us; SIMULATION_INPUT_FILE = vmefpga9.scf; CHECK_OUTPUTS = OFF; USE_DEVICE = OFF; SETUP_HOLD = OFF; OSCILLATION = OFF; OSCILLATION_TIME = 0.0ns; GLITCH = OFF; GLITCH_TIME = 0.0ns; START_TIME = 0.0ns; BIDIR_PIN = STRONG; END; TIMING_ANALYZER_CONFIGURATION BEGIN ANALYSIS_MODE = REGISTERED_PERFORMANCE; AUTO_RECALCULATE = OFF; CUT_OFF_IO_PIN_FEEDBACK = ON; CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; LIST_ONLY_LONGEST_PATH = ON; CELL_WIDTH = 18; DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; INCLUDE_PATHS_GREATER_THAN = OFF; INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; INCLUDE_PATHS_LESS_THAN = OFF; INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; LIST_PATH_COUNT = 10; LIST_PATH_FREQUENCY = 10MHz; CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; END; OTHER_CONFIGURATION BEGIN EXPLICIT_FAMILY = 1; COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; ORIGINAL_MAXPLUS2_VERSION = 9.3; ROW_PINS_PERCENT = 50; EXP_PER_LCELL_PERCENT = 100; FAN_IN_PER_LCELL_PERCENT = 100; LCELLS_PER_ROW_PERCENT = 100; LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; DEFAULT_9K_EXP_PER_LCELL = 1/2; FLEX_10K_52_COLUMNS = 40; LAST_MAXPLUS2_VERSION = 9.6; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = ON; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 BEGIN CASCADE_CHAIN = AUTO; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = AUTO; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 BEGIN CASCADE_CHAIN = MANUAL; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = MANUAL; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END;