%ttc_port is store ttc data in a lpm_ram and send them out in order
 according to VME command%
PARAMETERS (N=2); %N IS THE WIDTH OF LPM_RAM ADDERSS PORT%
FUNCTION lpm_ram_dp (wren, data[LPM_WIDTH-1..0], wraddress[LPM_WIDTHAD-1..0], wrclock,
                     rden, rdaddress[LPM_WIDTHAD-1..0], rdclock,rdclken)
	WITH (LPM_WIDTH=8, LPM_WIDTHAD= N, LPM_INDATA="REGISTERED")
	RETURNS (q[LPM_WIDTH-1..0]);

SUBDESIGN TTC_PORT3
(	CLK,                 %system clock%
    /RST,
    DI[31..0],            %TTC DATA FROM VME%
    VMEADD[13..6],        %VME ADDRESS AS COMMAND, FROM VME_PORT%
    ST5,               %SEQUENCE CONTROL FROM STATE MACHINE IN VME_PORT.TDF%
    TTC_FLG                %TMP%           %TTC FLAG FROM   ??%
                  :	INPUT;
    TTC_DAT[7..0],        %TTC DATA TO INPUTFPGA%
    TTC_BCIDWR,           %TTC BICD WRITE SIGNAL TO INPUTFPGA%
    TTC_TYPEWR,           % TTC TYPE WRITE SIGNAL TO INPUTFPGA%
    TTC_RSTN,              %NOT USED%
    FEB_FLG,               %A FLAG TO FEB_PORT  ??%
    BSY               %TTC BSY FLAG TO VMEPORT%
                  : OUTPUT;
)
variable
    LOAD		:NODE;
    SEND		:NODE;
    BUF         :LPM_RAM_DP;

    BYT[N-1..0]   :DFF;      %UNSTACK 32 BIT WORD TO 4 BYTES%
    WFRAME      :DFF;        %LPM_RAM.WEN%
    RACNT[1..0]   :DFF;      %BUF READ ADDRESS%
    PH    :DFF;              %FREE RUNNING DEVIDE BY 2 CLOCK%
    RCLK         :NODE;      %LPM_RAM'S READ CLOCK = PH.Q%
    RCNT[2..0]   :DFF;       %REEAD SEQUENCE%
    RFRAME        :DFF;      %LPM_RAM.REN%
    RCNTEN         :DFF;     %RCNT.EN%
    QQ[1..0]            :DFF; %USED TO GENERATE BCIDWR AND TYPEWR%

BEGIN

    %TTC PORT IS SELECTED%
     LOAD = (VMEADD[9..6] == 0) & (VMEADD[13..11] == 4);
     SEND = (VMEADD[9..6] == 1) & (VMEADD[13..11] == 4);  

    %unstack 31 bit vme data to 4 bytes ttc_dat AND WRITE INTO RAM%
     WFRAME.CLK = !CLK;
     WFRAME.D   = LOAD & ST5 # WFRAME & !(BYT[] == 3);

     BYT[N-1..0].CLK = !CLK;  BYT[].CLRN = /RST;
     IF WFRAME THEN 
       BYT[].D = BYT[].Q + 1;
      ELSE BYT[].D = GND;
     END IF;

    BUF.WRCLOCK  = CLK;
    BUF.WREN     = WFRAME.Q;
    BUF.WRADDRESS[N-1..0]  = BYT[].Q;
    BUF.DATA[7..0]     = (BYT[] == 0) & DI[7..0] # (BYT[]==1) & DI[15..8]
                         # (BYT[]==2) & DI[23..16]  # (BYT[]==3) & DI[31..24];

    
    %SEND TTC DATA %

        %RCLOCK%
      PH.CLK = CLK;
      PH.D =  !PH.Q;
      
      RCLK = PH.Q;

       % READ ADDRESS%
      RFRAME.CLK = CLK; 
      RFRAME.D   = SEND & ST5 # RFRAME & !(RCNT[]==7);
      RCNTEN.CLK = !RCLK;
      RCNTEN.D = RFRAME;
      RCNT[].CLK = !RCLK;
      IF RCNT[].Q == 7 THEN
         RCNT[].D = GND;
       ELSIF RCNTEN.Q THEN
        RCNT[].D  = RCNT[].Q + 1;
       ELSE RCNT[].D = RCNT[].Q;
      END IF;
     
      RACNT[1..0].CLK  = !RCLK;
      IF RCNT[].Q==7 THEN
         RACNT[].D = GND;
       ELSIF RCNTEN & RFRAME & (RCNT[]!=3) & (RCNT[]!=4) & (RCNT[]!=5)
                      & (rcnt[] !=7) &  (RCNT[] !=6) THEN
          RACNT[].D = RACNT[].Q +1;
       ELSE RACNT[].D = racnt[].q;
      END IF;
      
    %BUF READ%
     BUF.RDCLOCK   = RCLK; BUF.RDCLKEN = VCC;
     BUF.RDEN      = RFRAME & (RCNT[]!=3) & (RCNT[]!=4) & (RCNT[]!=5) & (rcnt[]!=7);
     BUF.RDADDRESS[N-1..0] = RACNT[1..0];
     TTC_DAT[7..0] = BUF.Q[7..0];
    %TTC_BCIDWR AND TTC_TYPEWR%
     QQ[1..0].CLK = RCLK;
     QQ0.D = (RCNT[].Q==1) # QQ0.Q & !(RCNT[].Q==4);
      TTC_BCIDWR = QQ0 & !RCLK;
      
      QQ1.D = (RCNT[]==7); 
      TTC_TYPEWR = QQ1.Q & !RCLK;
      TTC_RSTN = VCC;
     %TTC BSY%
      BSY = WFRAME # RFRAME;  
       FEB_FLG = GND;
 END;