%sub file of vmefpga1                modified on 10/5/2000%
PARAMETERS (DEPTH1 = 10, DEPTH2 = 8); 

FUNCTION lpm_counter ( data[lpm_width-1..0], clock, cnt_en, updown,sclr, aclr, sload)
   WITH (LPM_WIDTH, CARRY_CNT_EN= "SMART")
   RETURNS (q[LPM_WIDTH-1..0], cout, eq[1..0]);

SUBDESIGN FEB_PORT_new1     %MODIFIED TO load and send test data to muxfpga 9/26/00% 
( clk,         		       %40 mhz system clock%
  /RST,        		       %SOFT RESET FROM VME_PORT.TDF%
  DI[31..0],   		       %FEB DATA or SEND control data from VME%
  VMEADD[13..6],  	       %RETIMED VME ADDRESS AS VME COMMAND, FROM VME_PORT.TDF%
  ST9,ST6 ,ST10,           %SEQUENCE CONTROL%
  DOUBLE,                   %DOUBLE FRAME FLAG%
  mux_r_bsy                %read busy signal from muxfpga%            
               :INPUT;
  DO[15..0],               %test DATA TO MUXFPGA%
  BSY,                     %WRITE OR READ IS BUSY, TO VME_PORT.TDF%
  FEB_STATUS[31..0],       %STAUS TO VME_PORT%
  TFLAG,                   %SEND WITH TTC FLAG, TO TTC_PORT%
  MUXload,                 %a pulse TO GENERATE lpm_ram.WE IN MUXFPGA%
  MUXsend                  %A PULSE TO MUXFPGA, to initiate ram read%
              :OUTPUT;
)
VARIABLE
    
 WACNT               :LPM_COUNTER WITH (LPM_WIDTH = DEPTH1); %LPM_RAM WADDRESS COUNTER%
 load                : node; %VME COMMAND, LOAD FEB DATA%
 send                : node; %VME COMMAND, SEND FEB DATA%
 SEL                 :NODE; %ASSERTED WHEN FEB_PORT IS SELECTED%
 STAT                :NODE; %ASSERTED WHEN VME WANTS TO READ FEB STORAGE STATUS%
 STATUS[31..0]       :DFFE;  %LPM_FIFO STATUS TO VME%
 WREG[9..0]          :DFFE; %RECORD written words number%
 TREG[DEPTH2..0]     :DFFE;  %RECORD SENDING TIMES AND TTC FLG%
 
BEGIN
        %FEB PORT SELECTED%
        SEL = (VMEADD[13..11]==3);
        LOAD = (VMEADD[9..6]==0) & SEL;
        SEND = (VMEADD[9..6]==1) & SEL;   
        STAT = (VMEADD[9..6]==2) & SEL;
       

        
        %LPM_RAM WRITE ADDRESS %
        %ALWAYS RESET WACNT BEFORE LOAD%
         WACNT.CLOCK    = CLK;  WACNT.SCLR = !/RST;
         WACNT.UPDOWN = VCC;
         WACNT.SLOAD  = GND;       
         WACNT.DATA[9..0] = GND;        % % 
         WACNT.CNT_EN  = load & ST10;
 
         WREG[].CLK = CLK; WREG[].CLRN = /RST;
         WREG[].ENA = SEND & ST9;
         WREG[].D   = WACNT.Q[] -1;  
         
         %sending time recorder%
         TREG[DEPTH2..0].CLK   = CLK;
         TREG[].ENA   = SEND & ST9;
         TREG[DEPTH2-1..0].D     = DI[DEPTH2-1..0];  %record FEB data sending times%
         %ttc flag recorder ??%
         TREG[DEPTH2].D          = DI[30];           %RECORD TTC FLAG%
         TFLAG = TREG[DEPTH2].Q;
               
        %STATUS WORD%
        STATUS[].CLK 	=  CLK;
        STATUS[].ENA 	= STAT & ST6;
        STATUS[9..0].D 	= WREG[].Q;                 %THE # OF WORDS STORED IN THE ram%
        STATUS[10].D    = mux_r_bsy ;              % FEB DATA IN READING PROCESS %
        STATUS[11].D    = WACNT.COUT;              %WACNT OVERFLOW%
        STATUS[12].D    = st9 & load # mux_r_bsy;  %FEB_PORT IS BUSY%
        STATUS[DEPTH2+13..13].D    = TREG[DEPTH2..0].Q; %SENDING TIMES ISSUED BY VME%
        STATUS[DEPTH2+14].D        = DOUBLE;  		%double frame flag%     
        STATUS[31..DEPTH2+15].D    = GND ; 
        FEB_STATUS[31..0]   = STATUS[].Q;
        %FEB_PORT BUSY%
        BSY = mux_r_bsy # ST9 & LOAD;
        %OUTPUT TO MUXFPGA%
        MUXLOAD = LOAD & st9; 
        MUXSEND = SEND & ST9;
        DO[15..0] = (LOAD # SEND) & DI[15..0];
END;