PARAMETERS (DEPTH1 = 10, DEPTH2 = 8); % DEPTH IS THE WIDTH OF LPM_RAM ADDRESS PORTS% FUNCTION lpm_ram_dp (wren, data[LPM_WIDTH-1..0], wraddress[LPM_WIDTHAD-1..0], wrclock, rden, rdaddress[LPM_WIDTHAD-1..0], rdclock) WITH (LPM_WIDTH=16, LPM_WIDTHAD=DEPTH1, LPM_INDATA="REGISTERED") RETURNS (q[LPM_WIDTH-1..0]); FUNCTION lpm_counter ( data[lpm_width-1..0], clock, cnt_en, updown,sclr, aclr, sload) WITH (LPM_WIDTH, CARRY_CNT_EN= "SMART") RETURNS (q[LPM_WIDTH-1..0], cout, eq[1..0]); SUBDESIGN FEB_PORT3 % 5/17/00% ( clk, %40 mhz system clock% /RST, %SOFT RESET FROM VME_PORT.TDF% DI[31..0], %FEB DATA or SEND control data from VME% VMEADD[13..6], %RETIMED VME ADDRESS AS VME COMMAND, FROM VME_PORT.TDF% ST9,ST6 ,ST10 %SEQUENCE CONTROL% :INPUT; DO[15..0], %DATA TO INPUTFPGA% BSY, %WRITE TO OR READ FROM BUF IS BUSY, TO VME_PORT.TDF% FEB_STATUS[31..0], %STAUS TO VME_PORT% TFLAG %SEND WITH TTC FLAG, TO TTC_PORT% :OUTPUT; ) VARIABLE BUF :LPM_RAM_DP; %STORE VME LOADED FEB DATA % WACNT :LPM_COUNTER WITH (LPM_WIDTH = DEPTH1); %LPM_RAM WADDRESS COUNTER% RACNT :LPM_COUNTER WITH (LPM_WIDTH = DEPTH1); %LPM_RAM RADDRESS COUNTER% TCNT :LPM_COUNTER WITH (LPM_WIDTH = DEPTH2); %SEND TIMES COUNTER% SEL :NODE; %ASSERTED WHEN FEB_PORT IS SELECTED% LOAD :NODE; %ASSERTED WHEN VME WANTS TO WRITE FEB DATA TO BUF% SEND :NODE; %ASSERTED WHEN VME WANTS TO SEND FEB DATA OUT% STAT :NODE; %ASSERTED WHEN VME WANTS TO READ FEB STORAGE STATUS% STATUS[31..0] :DFFE; %LPM_FIFO STATUS TO VME% RFRAME :NODE ;%% WREG[9..0] :DFFE; %RECORD # OF WORD IN buf FROM VME WRITE% TREG[DEPTH2..0] :DFFE; %RECORD SENDING TIMES AND TTC FLG% BEGIN %FEB PORT SELECTED% SEL = (VMEADD[13..11]==3); LOAD = (VMEADD[9..6]==0) & SEL; SEND = (VMEADD[9..6]==1) & SEL; STAT = (VMEADD[9..6]==2) & SEL; %STORE FEB DATA INTO BUF% BUF.WRCLOCK = CLK; BUF.WREN = LOAD & ST9; BUF.DATA[15..0] = LOAD & DI[15..0]; BUF.WRADDRESS[9..0] = WACNT.Q[9..0]; %READ FEB DATA OUT OF BUF% BUF.RDCLOCK = CLK; BUF.RDEN = RFRAME; BUF.RDADDRESS[9..0] = RACNT.Q[9..0]; DO[15..0] = BUF.Q[15..0]; %LPM_RAM WRITE ADDRESS % %ALWAYS RESET WACNT BEFORE LOAD% WACNT.CLOCK = CLK; WACNT.SCLR = !/RST; WACNT.UPDOWN = VCC; WACNT.SLOAD = GND; WACNT.DATA[9..0] = GND; % % WACNT.CNT_EN = LOAD & ST10; WREG[].CLK = CLK; WREG[].CLRN = /RST; WREG[].ENA = SEND & ST9; WREG[].D = WACNT.Q[] -1; %LPM_RAM READ ADDRESS % RACNT.CLOCK = CLK; RACNT.SCLR = !/RST; RACNT.UPDOWN = VCC; RACNT.SLOAD = ST9 & SEND # (WREG[].Q == RACNT.Q[]) & RFRAME; RACNT.DATA[9..0] = GND; % % RACNT.CNT_EN = RFRAME; %READ FRAME% RFRAME = (TCNT.Q[] !=0); %SEND TIMES CONTROL% TCNT.CLOCK = CLK; TCNT.SCLR = !/RST; TCNT.UPDOWN = GND; TCNT.SLOAD = SEND & ST9; TCNT.DATA[DEPTH2-1..0] = SEND & DI[DEPTH2-1..0]; %LOAD SEND TIME PARAMETER% TCNT.CNT_EN = RFRAME & (WREG[].Q == RACNT.Q[]); TREG[DEPTH2..0].CLK = CLK; TREG[].ENA = SEND & ST9; TREG[DEPTH2-1..0].D = DI[DEPTH2-1..0]; TREG[DEPTH2].D = DI[30]; %RECORD TTC FLAG% TFLAG = TREG[DEPTH2].Q; %STATUS WORD% STATUS[].CLK = CLK; STATUS[].ENA = STAT & ST6; STATUS[9..0].D = WREG[].Q; %THE # OF WORDS STORED IN THE BUF% STATUS[10].D = RFRAME ; %SENDING FEB DATA% STATUS[11].D = WACNT.COUT; %WACNT OVERFLOW% STATUS[12].D = BSY; %FEB_PORT IS BUSY% STATUS[DEPTH2+13..13].D = TREG[DEPTH2..0].Q; %SENDING TIMES ISSUED BY VME% STATUS[31..DEPTH2+14].D = GND ; FEB_STATUS[31..0] = STATUS[].Q; %FEB_PORT BUSY% BSY = RFRAME # ST9 & LOAD; END;