% subckt of dspoutfpga        The VME bus input port %
%MODIFIED FROM ORIGINAL VMEIN.TDF: CHANGES ON RDY logic      3/20/00%
SUBDESIGN   TVMEIN        %STACK 4-BYTE VME DATA TO A 32 BIT WORD%

              (CP,            % local 40 mhz clock                 %
               ADD[3..0],     % VME address                        %
               CS,            % VME PU select                      %
               R/W,           % VME read/write                     %
               DS,            % VME data strobe                    %
               DAT[7..0],     % VME data byte                      %
               
               SERBSY,     % the dsprec port is busy, set when REGA[] IN DSPREC IS NOT FREE%
               DPMBSY,     % the DPM serial port is busy, set during SD,SF shift out%
               CNFBSY      % the inputfpga config port is busy, set during data0 shifts out %
               :INPUT;
               
               RDY,        % the Ready to VME, PULLs LOW IF vme data has not been sent out %
               DO[31..0],  % the 32 bit word from VME                           %
               WRCNTL,     % writes data to the cntl register          if ADD=0 %
               WRSER,      % writes data to the DSP serial receiver    if ADD=1 %
               WRADD,      % writes DP memory address register         if ADD=2 %
               WRDAT,      % writes DP memory data, and inc address    if ADD=3 %
               WRCNF       % writes config data byte to the input fpga if ADD=4 %
               :OUTPUT;)
                
          VARIABLE
              BSY              :LCELL  ;
          
              REGA[7..0]       :DFFE   ;
              REGB[7..0]       :DFFE   ;
              REGC[7..0]       :DFFE   ;
              REGD[31..0]      :DFFE   ;
              CNT[1..0]        :DFF    ;  % counts the 4 input bytes %
              VALID            :DFF    ;
                           
              DSYNC[2..1]      :DFF    ;  % syncs the VME data to the local clock %
              LOAD             :DFF    ;
              SRHLD            :SRFF   ;  %IS SET WHEN VMEIN IS STACKING THE 4 
                                           CONSECUTIVE DATA BYTE%
              DELAY            : DFF;     %ONE CYCLE DELAY OF SRHLD%
              HOLD             :LCELL  ;  % = SRHLD.Q  # DELAY.Q%
            %  DDS              :DFF    ; % %SYNC DS TO LOCAL CLK CP%
              
          BEGIN
           %SYNC DS, SO THAT THE DATA TO OTHER SUCKTS ARE PROPERLY SYNCd TO CP %
           %   DDS.CLK = CP;%
           %   DDS.D   = DS;%
           % VME writes 4 data bytes to the processor: %
              CNT[].CLRN = CS  ;
              CNT[].CLK  = DS   ;
              IF !R/W THEN           % CNT[] ONLY COUNTS WHEN IT IS VME WRITE AND DS% 
              CNT[].D    = CNT[] + 1 ;
              ELSE CNT[] = CNT[].Q;
              END IF;
                         
              REGA[].CLK = DS ;
              REGB[].CLK = DS ;
              REGC[].CLK = DS ;
              REGD[].CLK = DS ;
              
              REGA[].ENA = CS & !R/W & (CNT[]==0) ;
              REGB[].ENA = CS & !R/W & (CNT[]==1) ;
              REGC[].ENA = CS & !R/W & (CNT[]==2) ;
              REGD[].ENA = CS & !R/W & (CNT[]==3) ;
              
              REGA[7..0].D   = DAT[]  ;
              REGB[7..0].D   = DAT[]  ;
              REGC[7..0].D   = DAT[]  ;
              REGD[7..0].D   = DAT[]  ;
              REGD[15..8].D  = REGC[] ;
              REGD[23..16].D = REGB[] ;
              REGD[31..24].D = REGA[] ;
              DO[]           = REGD[] ;
              
           % synchronize LOAD ENABLE from VME to the local clock: %
              VALID.CLK  = DS          ;
              VALID.D    = (CNT[]==3) #
                           VALID       ;
              VALID.CLRN = !LOAD       ;
           
              DSYNC[].CLK   = CP     ;
              DSYNC1.D      = VALID  ;
              DSYNC2.D      = DSYNC1 ;
              DSYNC[].CLRN  = !LOAD  ;

              LOAD.CLK     = CP             ;
              LOAD.D       = DSYNC2 & VALID ;

            % write the data to the addressed port: %
                                       
              WRCNTL = LOAD & (ADD[]==0) ;
              WRSER  = LOAD & (ADD[]==1) ;
              WRADD  = LOAD & (ADD[]==2) ;
              WRDAT  = LOAD & (ADD[]==3) ;
              WRCNF  = LOAD & (ADD[]==4) ;
              
            % inhibit the RDY to VME until the addressed port can accept new data: %
              SRHLD.CLK    = CP; SRHLD.CLRN = CS;
              SRHLD.S      = DS & !R/W;
              SRHLD.R      = LOAD;
              DELAY.CLK    = CP;
              DELAY.D      = SRHLD.Q;
              HOLD         = SRHLD.Q # DELAY.Q; 
             % BSY = (ADD[]==1) & (SERBSY # HOLD) #
                          (ADD[]==3) & (DPMBSY # HOLD) #
                          (ADD[] == 4) & (CNFBSY # HOLD) ;%
              BSY = SERBSY # DPMBSY # CNFBSY # HOLD;     %NEW, NO NEED TO AND ADD[] == X%
              RDY = !BSY ; 
              
              END ;