%SUBSCKT OF DSPOUTFPGA    RECEIVES DSP XMT SERIAL DATA FOR VME OUT PORT  July 19'00%
%NEW VERSION %

SUBDESIGN  TDSPXMT
                    (%CP,      % % the local 40 mhz clock           %
                     DX,       % the DSP serial xmt data          %
                     SFX,      % the DSP serial xmt frame         %
                     CLKX,     % the DSP serial xmt clock         %
                     SELSERR,  % VMEOUT selects output data       %
                     RSTSERR   % VMEout resets the data ready flag after read%
                     :INPUT;
                     SER2VMERDY,% THE DATA RDY STATUS               %
                     IRQ1,      %INTERRUPT TO VME, GOES TO CTLSTAT.TDF%
                     OVF,   %OVF IS SET WHEN NEXT FSX COMES BEFORE THE DSR DATA LOAD INTO DREG%
                     DO[31..0] % THE DATA TO VMEOUT                %
                     : OUTPUT;)

VARIABLE

                   DSR[31..0]	:DFFE;         %SERIAL DATA SHIFT REG.%
                   FSR[30..0]	:DFFE;         %SERIAL FRAME SHIFT REG.%
                   DREG[31..0]  : DFFE;        %SECOND DATA REG.%
                   SRRDY        : SRFF;        %GENERATE SER2VMERDY STATUS%
                   RSTSYNC      :DFF;          %SYNC. RSTSERR TO CLKX     %
                   SROVF        : SRFF;        %OVF STATUS REGISTER%
                   S:	machine of bits (sb[1..0]) with states (
                S0 = B"00",
                S1 = B"01",
                S2 = B"10",
                S3 = B"11");


BEGIN
             
              % the DSP sends the framed 32 bit data FROM SERIAL XMT port %
                 DSR[].CLK    = CLKX       ;
                 DSR[].ENA    = S0 # S1    ;
                 DSR0.D       = DX         ;
                 DSR[31..1].D = DSR[30..0] ;
                 
                 FSR[].CLK    = CLKX       ;
                 FSR[].ENA    = S0 # S1    ;
                 FSR0.D       = SFX        ;
                 FSR[30..1].D = FSR[29..0] ;
     
              %DATA LOAD CONTROL %
                  S.CLK = CLKX;
              CASE S IS 
                WHEN S0 =>
                  IF FSR[30] THEN
                     S = S1;
                  END IF;
                WHEN S1 =>
                  IF !SER2VMERDY THEN
                     S = S2;               %LOAD DATA TO DREG%
                  ELSE S = S3;
                  END IF;
                WHEN S2 =>
                   S = S0;
                WHEN S3 =>
                   IF !SER2VMERDY THEN
                   S = S2;
                   ELSE S = S3;           
                   END IF;
               END CASE;
   
              %LOAD DATA TO OUT REG %

                DREG[].CLK = CLKX; DREG[].CLRN = !(RSTSYNC.Q & SRRDY.Q);
                DREG[].ENA = S2;
                DREG[].D   = DSR[].Q;
                DO[]       = SELSERR & DREG[].Q;
              
              %DATA RDY TO VME FLAG %
                RSTSYNC.CLK = CLKX;
                RSTSYNC.D   = RSTSERR;

                SRRDY.CLK = CLKX;
                SRRDY.S    = S1;
                SRRDY.R    = RSTSYNC.Q;
                SER2VMERDY = SRRDY.Q;

              % IRQ1 TO INTERRUPT VME, CONNECT TO INT7%
                IRQ1       = DO[31];
              % OVF FLAG TO STATUS %
                SROVF.CLK  = CLKX;
                SROVF.S    = S3 & SFX;
                SROVF.R    = (S != S3);
                OVF        = SROVF.Q;  
END;