% sends data from VME to the DSP serial receiver port % SUBDESIGN TDSPREC %NEW VERSION 3/16/00% (CP, % the local 40 mhz clock % DI[31..0], % data from VME % WRSER % load and send VME data % :INPUT; CLKR, % clock to the DSP serial port % FSR, % the frame to the DSP serial port % DR, % the data to the DSP serial port % SERBSY %BUSY FLAG TO VMEIN WHEN REGA[] IS NOT FREE% :OUTPUT;) VARIABLE LOADA : LCELL ; LOADB : LCELL ; REGA[31..0] :DFFE ; REGB[31..0] : DFF ; SEND : DFF ; CNT[5..0] : DFF ; SRBUSY : SRFF ; %SERBSY FLAG TO VMEIN% S: machine of bits (sb[1..0]) with states ( S0 = B"00", S1 = B"01", S2 = B"10", S3 = B"11"); BEGIN %LOAD CONTROL% S.CLK = CP; CASE S IS WHEN S0 => IF WRSER & !SEND THEN S =S1; %LOADB% ELSIF WRSER & SEND THEN S =S2; ELSE S = S0; END IF; WHEN S1 => S = S0; WHEN S2 => %WRSER OCCURES DURING SEND, WAIT FOR CNT[] == 32, THEN LOADB% IF SEND & CNT[] == 32 # !send THEN S = S1; ELSE S = S2; END IF; END CASE; LOADA = WRSER; LOADB = S1; SEND.CLK = CP; SEND.D = LOADB # SEND & !(CNT[]==32); CNT[].CLK = CP; IF CNT[] == 32 THEN CNT[].D = 0 ; ELSIF SEND THEN CNT[].D = CNT[] + 1 ; ELSE CNT[].D = CNT[] ; END IF ; %LOAD AND SHIFT OUT VME WRITE DATA % REGA[31..0].CLK = CP; REGA[].D = DI[]; REGA[].ENA = LOADA; REGB[].CLK = CP; REGB[].D = REGA[].Q & LOADB ; REGB[31..1].D = !LOADB & REGB[30..0].Q; DR = REGB[31]; FSR = LOADB; CLKR = CP; %SERBSY FLAG% SRBUSY.CLK = CP; SRBUSY.S = LOADA; SRBUSY.R = LOADB; SERBSY = SRBUSY.Q; END;