% ATLAS\ROD\OUTPUT\TDSPOUTFPGA EPF10K30EEQC208-2 AUG 15'00 % %SEPT 24'00% %modified from original dspoutfpga 3/24/00% %modified from /out6/tdspoutfpga1, changes only in test point 5/30/00% % The DSPOUTFPGA interfaces to the VME control bus, to the DSPINFPGA configuration pins, to the DSPINFPGA serial receiver, to the DSP I/O flags, to the DSP serial receiver, to the DSP serial transmitter, to the DSP expansion bus buffer, to the output FIFO. % FUNCTION TVMEIN (ADD[3..0],CS,R/W,DS,DAT[7..0],CP,SERBSY,DPMBSY,CNFBSY) RETURNS (RDY,DO[31..0],WRCNTL,WRSER,WRADD,WRDAT,WRCNF) ; FUNCTION TVMEOUT1 (CP,DI[31..0],BUFRDY,SERRDY,CS,R/W,ADD[3..0]) RETURNS (DSO,RDY,DAT[7..0], SELSTAT,SELBUF,RDBUF,SELSERR,RSTSERR, SELCNTL) ; FUNCTION TCNTLSTAT (CP,DI[9..0],WRCNTL,SELSTAT,SELCNTL,NSTATUS,CONF_DONE, BUFFULL,BUFEF,BUFWDCNT[8..0],FIFOAF,FIFOEF,FIFOFF, BUSY,FSX1,DX1_IN,SERRDY, serrovf, irq1,EVENT[7..0]) RETURNS (/RSTDSP,/RSTFIFO,/RSTBUF,/OFFLINE,NCONFIG,FLAGI[2..1],DO[31..0]) ; FUNCTION TCONFIG (CP,WRCNF,DI[7..0]) RETURNS (CNFBSY,DAT0,DCLK) ; FUNCTION TDPMSERW (CP,DI[31..0],WRADD,WRDAT) RETURNS (DPMBSY,SDH,SDL,SAD,SFR) ; FUNCTION TDSPREC (CP,DI[31..0],WRSER) RETURNS (SERBSY,CLKR,FSR,DR) ; FUNCTION TDSPXMT (DX,SFX,CLKX,SELSERR,RSTSERR) RETURNS (SER2VMERDY,IRQ1, OVF,DO[31..0]) ; FUNCTION TDSPBUF (CP,/RSTBUF,RDBUF,SELBUF,XFCLK,/XCE1,XD[31..0]) RETURNS (BUFRDY,EF,HF,FULL,DO[31..0],BUFWDCNT[8..0]) ; FUNCTION TDSPFIFO (CP,XFCLK,XD[31..0],/XCE2,/RSTFIFO,DMAC,FIFO_EVTEND) RETURNS (DO[31..0],/WEN,WCLK,/MR,FIFO_EVTRDY,EVENT[7..0]) ; SUBDESIGN TDSPOUTFPGA2( CP, % the local 40 mhz clock % CS, % VME selects the processor % R/W, % VME read/write direction % ADD[3..0], % VME address to the processor % DS % the data byte strobe from VME % :INPUT; DAT[7..0] % the data byte from/to VME % :BIDIR; RDY, % the PU ready to VME % DSO % the output DS to VME % :OUTPUT; FSX1, % % BSYFLG, % the busy flag from the DSP % DX1_IN % INITIALIZE THE INPUT FPGA % :INPUT; DSPBUSY, % the DSP BUSY flag to the Level1 trigger % FSR[2..1], % % /RSTDSP, % async reset to the DSP % FSX2_OUT % % :OUTPUT; CLKR, % clock to the DSP serial receiver % FSR0, % frame to the DSP serial receiver % DR % data to the DSP serial receiver % :OUTPUT; DX, % the DSP serial xmt data % SFX, % the DSP serial xmt frame % CLKX % the DSP serial xmt clock % :INPUT; /OFFLINE, % offline to write to the input Dual Port % SAD, % the serial starting address to the DPM % SDL, % the serial data bits 15 to 0 to the DPM % SDH, % the serial data bits 31 to 16 to the DPM % SFR % writes data, inc's address for the frame % :OUTPUT; XFCLK, % the DSP expansion port output clock % /XCE[2..1], % the DSP expansion port output selects % XD[31..0] % the DSP expansion port output data % :INPUT; /EF, % the fifo empty flag % /PAF, % the fifo /PAF % /FF, % the fifo /ff % DMAC, % DMA frame comptete pulse from the DSP % FIFO_EVTEND % event read flag from the fifo readout % :INPUT; FIFOCLK, DO[31..0], % DSP data to the output fifo % /WEN, % DSP write enable to the output fifo % /MR, % async reset to the output fifo % FIFO_EVTRDY % event ready to the fifo readout % :OUTPUT; NSTATUS, % nstatus from the input fpga % CONF_DONE % conf_done from the input fpga % :INPUT; NCONFIG, % nconfig to the input fpga % CNF_DAT0, % dat0 to the input fpga % CNF_DCLK % dclk to the input fpga % :OUTPUT; IRQ1, % DSPXMT INTERRUPT TO VME % IRQ2, % % INT7, % VME INTERRUPT % INT6, % FIFO AF INTERRUPT % INT5 % BUF HF INTERRUPT % :output; V_XX, % FROM 7K CHIP % INPUT_RDY % FROM INPUT FPGA % :INPUT; INITIALIZE % TO INPUT FPGA % :OUTPUT; TESTPT1, % TESTPOINT 1 % TESTPT2, % TESTPOINT 2 % TESTPT3, % TESTPOINT 3 % TESTPT4, % TESTPOINT 4 % TESTPT5, % TESTPOINT 5 % TESTPT6, % TESTPOINT 6 % TESTPT7, % TESTPOINT 7 % TESTPT8 % TESTPOINT 8 % :OUTPUT;) VARIABLE VMEI :TVMEIN ; VMEO :TVMEOUT1 ; CNTL :TCNTLSTAT; REC :TDSPREC ; XMT :TDSPXMT ; BUF :TDSPBUF ; OUT :TDSPFIFO ; CNF :TCONFIG ; %SAME AS ZCONFIG0% DPM :TDPMSERW ; SYNC_DS :DFF; %SYNC INPUT DS TO LOCAL 40 MHZ CLK% SYNC_DAT[7..0] :DFF; %SYNC INPUT DAT[7..0] TO 40 MHZ LOCAL CLK% SYNC_R/W :DFF; %SYNC INPUT R/W TO CP% SYNC_ADD[3..0] :DFF; %SYNC INPUT ADD[] TO CP% BEGIN % --- INITIALIZE THE INPUT FPGA FROM THE DSP:% INITIALIZE = DX1_IN ; % --- the VME input port: % SYNC_DS.CLK = CP; SYNC_DS.D = DS; SYNC_DAT[].CLK = CP; SYNC_DAT[].D = DAT[]; SYNC_ADD[].CLK = CP; SYNC_ADD[].D = ADD[]; SYNC_R/W.CLK = CP; SYNC_R/W.D = R/W; VMEI.CP = CP ; VMEI.CS = CS ; VMEI.R/W = SYNC_R/W ; VMEI.ADD[] = SYNC_ADD[] ; VMEI.DAT[] = SYNC_DAT[] ; VMEI.DS = SYNC_DS ; RDY = VMEI.RDY & VMEO.RDY; %NEW% % --- BOTH VME IN/OUT SHOULD BE RDY BEFORE NEW VME OPERATION BEGINS% VMEI.SERBSY = REC.SERBSY ; VMEI.DPMBSY = DPM.DPMBSY ; VMEI.CNFBSY = CNF.CNFBSY ; CNTL.WRCNTL = VMEI.WRCNTL ; REC.WRSER = VMEI.WRSER ; DPM.WRADD = VMEI.WRADD ; DPM.WRDAT = VMEI.WRDAT ; CNF.WRCNF = VMEI.WRCNF ; REC.DI[] = VMEI.DO[] ; DPM.DI[] = VMEI.DO[] ; % --- The VME output port: % VMEO.CP = CP ; VMEO.CS = CS ; VMEO.R/W = R/W ; VMEO.ADD[] = ADD[] ; DSO = VMEO.DSO ; DAT[7..0] = VMEO.DAT[] ; VMEO.BUFRDY = BUF.BUFRDY ; VMEO.SERRDY = XMT.SER2VMERDY ; CNTL.SELSTAT = VMEO.SELSTAT ; CNTL.SELCNTL = VMEO.SELCNTL ; XMT.SELSERR = VMEO.SELSERR ; XMT.RSTSERR = VMEO.RSTSERR ; % --- The status/control port: % VMEO.DI[31..0] = CNTL.DO[31..0] ; CNTL.DI[9..0] = VMEI.DO[9..0] ; CNTL.EVENT[7..0] = OUT.EVENT[7..0] ; CNTL.CP = CP ; CNTL.DX1_IN = DX1_IN ; CNTL.SERRDY = XMT.SER2VMERDY ; CNTL.FIFOEF = !/EF ; CNTL.FIFOAF = !/PAF ; CNTL.FIFOFF = !/FF ; CNTL.BUSY = BSYFLG ; CNTL.FSX1 = FSX1 ; CNTL.SERROVF = XMT.OVF ; CNTL.IRQ1 = XMT.IRQ1 ; FSX2_OUT = VMEO.RSTSERR ; %?% /OFFLINE = CNTL./OFFLINE ; /RSTDSP = CNTL./RSTDSP ; FSR[2..1] = CNTL.FLAGI[] ; % --- The serial write port to the DSP serial receiver: % REC.CP = CP ; CLKR = REC.CLKR ; FSR0 = REC.FSR ; DR = REC.DR ; % --- The serial read port from the DSP serial xmitter: % XMT.DX = DX ; XMT.SFX = SFX ; XMT.CLKX = CLKX ; VMEO.DI[] = XMT.DO[] ; IRQ1 = XMT.IRQ1 ; %NEW% % --- The extension port buffer to VMEOUT: % BUF./RSTBUF = CNTL./RSTBUF ; BUF.XFCLK = XFCLK ; BUF./XCE1 = /XCE1 ; BUF.XD[] = XD[] ; BUF.CP = CP ; BUF.SELBUF = VMEO.SELBUF ; BUF.RDBUF = VMEO.RDBUF ; VMEO.DI[] = BUF.DO[] ; CNTL.BUFFULL = BUF.FULL ; CNTL.BUFEF = BUF.EF ; CNTL.BUFWDCNT[] = BUF.BUFWDCNT[] ; % --- The fifo output port: % OUT./RSTFIFO = CNTL./RSTFIFO ; OUT.XFCLK = XFCLK ; OUT.XD[] = XD[] ; OUT./XCE2 = /XCE2 ; /WEN = OUT./WEN ; DO[] = OUT.DO[] ; /MR = OUT./MR ; FIFOCLK = XFCLK ; OUT.CP = CP ; OUT.DMAC = DMAC ; OUT.FIFO_EVTEND = FIFO_EVTEND ; FIFO_EVTRDY = OUT.FIFO_EVTRDY ; % ---------------------------------------------------------------------- % % --- The configuration port for the input fpga: % CNTL.NSTATUS = NSTATUS ; CNTL.CONF_DONE = CONF_DONE ; CNF.CP = CP ; CNF.DI[7..0] = VMEI.DO[7..0] ; NCONFIG = CNTL.NCONFIG ; CNF_DAT0 = CNF.DAT0 ; CNF_DCLK = CNF.DCLK ; % --- The Dual Port Memory serial port for loading files to the DSP: % DPM.CP = CP ; SAD = DPM.SAD ; SDL = DPM.SDL ; SDH = DPM.SDH ; SFR = DPM.SFR ; % --- INTERRUPTS TO THE DSP: % INT7 = CNTL.FLAGI1 ; INT6 = !/PAF ; INT5 = BUF.HF ; DSPBUSY = BSYFLG ; IRQ2 = GND ; % --- TESTPOINT OUTPUTS: % TESTPT1 = vcc; TESTPT2 = /WEN; %OUTPUT FIFO WRITE ENABLE% TESTPT3 = FSX1; %DSP PULL THE FLG HIGH AFTER BEING BOOTED% %fsr,frame to dsp serial receiver% TESTPT4 = DO[0]; %EXPANSION BUS DATA0 OUTPUT% TESTPT5 = /xce1; %DX% TESTPT6 = /xce2; %DR% TESTPT7 = /rstdsp; TESTPT8 = rdy; %pu_rdy TO OUTFPGA% END;