-- -- Copyright (C) 1988-2000 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. -- CHIP tdspoutfpga2 BEGIN |XD31 : INPUT_PIN = 186; |XD30 : INPUT_PIN = 187; |XD29 : INPUT_PIN = 190; |XD28 : INPUT_PIN = 191; |XD27 : INPUT_PIN = 189; |XD26 : INPUT_PIN = 193; |XD25 : INPUT_PIN = 195; |XD24 : INPUT_PIN = 192; |XD22 : INPUT_PIN = 200; |XD21 : INPUT_PIN = 197; |XD19 : INPUT_PIN = 204; |XD18 : INPUT_PIN = 199; |XD17 : INPUT_PIN = 202; |XD16 : INPUT_PIN = 205; |XD15 : INPUT_PIN = 206; |XD14 : INPUT_PIN = 203; |XD13 : INPUT_PIN = 207; |XD12 : INPUT_PIN = 208; |XD11 : INPUT_PIN = 8; |XD10 : INPUT_PIN = 7; |XD9 : INPUT_PIN = 9; |XD8 : INPUT_PIN = 11; |XD7 : INPUT_PIN = 14; |XD6 : INPUT_PIN = 10; |XD5 : INPUT_PIN = 12; |XD4 : INPUT_PIN = 16; |XD3 : INPUT_PIN = 13; |XD2 : INPUT_PIN = 15; |XD1 : INPUT_PIN = 17; |IRQ2 : OUTPUT_PIN = 164; |XD0 : INPUT_PIN = 18; |XD23 : INPUT_PIN = 196; |XD20 : INPUT_PIN = 198; |FSX2_OUT : OUTPUT_PIN = 139; |FSR2 : OUTPUT_PIN = 147; |FSR1 : OUTPUT_PIN = 143; |FSR0 : OUTPUT_PIN = 132; |FSX1 : INPUT_PIN = 140; |INITIALIZE : OUTPUT_PIN = 119; |V_XX : INPUT_PIN = 177; |INPUT_RDY : INPUT_PIN = 111; |DX1_IN : INPUT_PIN = 144; |TESTPT8 : OUTPUT_PIN = 176; |TESTPT7 : OUTPUT_PIN = 175; |TESTPT6 : OUTPUT_PIN = 174; |TESTPT5 : OUTPUT_PIN = 173; |TESTPT4 : OUTPUT_PIN = 170; |TESTPT3 : OUTPUT_PIN = 169; |TESTPT2 : OUTPUT_PIN = 168; |TESTPT1 : OUTPUT_PIN = 167; |CONF_DONE : INPUT_PIN = 161; |NSTATUS : INPUT_PIN = 160; |NCONFIG : OUTPUT_PIN = 159; |CNF_DAT0 : OUTPUT_PIN = 158; |CNF_DCLK : OUTPUT_PIN = 157; |/XCE2 : INPUT_PIN = 148; |/XCE1 : INPUT_PIN = 150; |/RSTDSP : OUTPUT_PIN = 142; |CLKR : OUTPUT_PIN = 134; |SFX : INPUT_PIN = 131; |DX : INPUT_PIN = 128; |DR : OUTPUT_PIN = 127; |INT7 : OUTPUT_PIN = 126; |BSYFLG : INPUT_PIN = 125; |INT6 : OUTPUT_PIN = 122; |INT5 : OUTPUT_PIN = 121; |DMAC : INPUT_PIN = 120; |SAD : OUTPUT_PIN = 116; |SDL : OUTPUT_PIN = 115; |SDH : OUTPUT_PIN = 114; |SFR : OUTPUT_PIN = 113; |/OFFLINE : OUTPUT_PIN = 112; |/PAF : INPUT_PIN = 103; |/FF : INPUT_PIN = 102; |/MR : OUTPUT_PIN = 101; |FIFOCLK : OUTPUT_PIN = 100; |/WEN : OUTPUT_PIN = 99; |DO0 : OUTPUT_PIN = 97; |DO1 : OUTPUT_PIN = 96; |DO2 : OUTPUT_PIN = 95; |DO3 : OUTPUT_PIN = 94; |DO4 : OUTPUT_PIN = 93; |DO5 : OUTPUT_PIN = 92; |DO6 : OUTPUT_PIN = 90; |DO7 : OUTPUT_PIN = 89; |DO8 : OUTPUT_PIN = 88; |DO9 : OUTPUT_PIN = 87; |DO10 : OUTPUT_PIN = 86; |DO11 : OUTPUT_PIN = 85; |DS : INPUT_PIN = 78; |DO12 : OUTPUT_PIN = 83; |DO13 : OUTPUT_PIN = 75; |DO14 : OUTPUT_PIN = 74; |DO15 : OUTPUT_PIN = 73; |DO16 : OUTPUT_PIN = 71; |DO17 : OUTPUT_PIN = 70; |DO18 : OUTPUT_PIN = 69; |DO19 : OUTPUT_PIN = 68; |DO20 : OUTPUT_PIN = 67; |DO21 : OUTPUT_PIN = 65; |DO22 : OUTPUT_PIN = 64; |DO23 : OUTPUT_PIN = 63; |DO24 : OUTPUT_PIN = 62; |DO25 : OUTPUT_PIN = 61; |DO26 : OUTPUT_PIN = 60; |DO27 : OUTPUT_PIN = 58; |DO28 : OUTPUT_PIN = 57; |do29 : OUTPUT_PIN = 56; |do30 : OUTPUT_PIN = 55; |do31 : OUTPUT_PIN = 54; |FIFO_evtrdy : OUTPUT_PIN = 53; |FIFO_evtend : INPUT_PIN = 47; |DSO : OUTPUT_PIN = 46; |DAT2 : BIDIR_PIN = 45; |CS : INPUT_PIN = 44; |RDY : OUTPUT_PIN = 39; |R/W : INPUT_PIN = 38; |DAT3 : BIDIR_PIN = 41; |DAT4 : BIDIR_PIN = 40; |DAT1 : BIDIR_PIN = 36; |DAT5 : BIDIR_PIN = 31; |DAT0 : BIDIR_PIN = 30; |DAT6 : BIDIR_PIN = 29; |ADD3 : INPUT_PIN = 28; |ADD2 : INPUT_PIN = 27; |ADD1 : INPUT_PIN = 26; |ADD0 : INPUT_PIN = 25; |DAT7 : BIDIR_PIN = 24; |DSPBUSY : OUTPUT_PIN = 19; |/EF : INPUT_PIN = 104; |IRQ1 : OUTPUT_PIN = 179; |clkx : INPUT_PIN = 182; |cp : INPUT_PIN = 184; |XFCLK : INPUT_PIN = 183; DEVICE = EPF10K30EQC208-2; END; DEFAULT_DEVICES BEGIN ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; AUTO_DEVICE = EPF10K30ETC144-1; AUTO_DEVICE = EPF10K30ETC144-1X; AUTO_DEVICE = EPF10K30EQC208-1; AUTO_DEVICE = EPF10K30EQC208-1X; AUTO_DEVICE = EPF10K30EFC256-1; AUTO_DEVICE = EPF10K30EFC256-1X; AUTO_DEVICE = EPF10K30EFC484-1; AUTO_DEVICE = EPF10K30EFC484-1X; AUTO_DEVICE = EPF10K50ETC144-1; AUTO_DEVICE = EPF10K50EQC208-1; AUTO_DEVICE = EPF10K50EQC240-1; AUTO_DEVICE = EPF10K50EFC256-1; AUTO_DEVICE = EPF10K50EFC484-1; AUTO_DEVICE = EPF10K50STC144-1; AUTO_DEVICE = EPF10K50STC144-1X; AUTO_DEVICE = EPF10K50SQC208-1; AUTO_DEVICE = EPF10K50SQC208-1X; AUTO_DEVICE = EPF10K50SQC240-1; AUTO_DEVICE = EPF10K50SQC240-1X; AUTO_DEVICE = EPF10K50SFC256-1; AUTO_DEVICE = EPF10K50SFC256-1X; AUTO_DEVICE = EPF10K50SBC356-1; AUTO_DEVICE = EPF10K50SBC356-1X; AUTO_DEVICE = EPF10K50SFC484-1; AUTO_DEVICE = EPF10K50SFC484-1X; AUTO_DEVICE = EPF10K100EQC208-1; AUTO_DEVICE = EPF10K100EQC208-1X; AUTO_DEVICE = EPF10K100EQC240-1; AUTO_DEVICE = EPF10K100EQC240-1X; AUTO_DEVICE = EPF10K100EFC256-1; AUTO_DEVICE = EPF10K100EFC256-1X; AUTO_DEVICE = EPF10K100EBC356-1; AUTO_DEVICE = EPF10K100EBC356-1X; AUTO_DEVICE = EPF10K100EFC484-1; AUTO_DEVICE = EPF10K100EFC484-1X; AUTO_DEVICE = EPF10K130EQC240-1; AUTO_DEVICE = EPF10K130EQC240-1X; AUTO_DEVICE = EPF10K130EBC356-1; AUTO_DEVICE = EPF10K130EBC356-1X; AUTO_DEVICE = EPF10K130EFC484-1; AUTO_DEVICE = EPF10K130EFC484-1X; AUTO_DEVICE = EPF10K130EBC600-1; AUTO_DEVICE = EPF10K130EBC600-1X; AUTO_DEVICE = EPF10K130EFC672-1; AUTO_DEVICE = EPF10K130EFC672-1X; AUTO_DEVICE = EPF10K200EGC599-1; AUTO_DEVICE = EPF10K200EBC600-1; AUTO_DEVICE = EPF10K200EFC672-1; AUTO_DEVICE = EPF10K200SRC240-1; AUTO_DEVICE = EPF10K200SRC240-1X; AUTO_DEVICE = EPF10K200SBC356-1; AUTO_DEVICE = EPF10K200SBC356-1X; AUTO_DEVICE = EPF10K200SFC484-1; AUTO_DEVICE = EPF10K200SFC484-1X; AUTO_DEVICE = EPF10K200SBC600-1; AUTO_DEVICE = EPF10K200SBC600-1X; AUTO_DEVICE = EPF10K200SFC672-1; AUTO_DEVICE = EPF10K200SFC672-1X; END; TIMING_POINT BEGIN DEVICE_FOR_TIMING_SYNTHESIS = EPF10K30EQC208-2; MAINTAIN_STABLE_SYNTHESIS = OFF; CUT_ALL_CLEAR_PRESET = ON; CUT_ALL_BIDIR = ON; END; IGNORED_ASSIGNMENTS BEGIN FIT_IGNORE_TIMING = ON; DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; IGNORE_DEVICE_ASSIGNMENTS = OFF; IGNORE_LC_ASSIGNMENTS = OFF; IGNORE_PIN_ASSIGNMENTS = OFF; IGNORE_CHIP_ASSIGNMENTS = OFF; IGNORE_TIMING_ASSIGNMENTS = OFF; IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; IGNORE_CLIQUE_ASSIGNMENTS = OFF; END; GLOBAL_PROJECT_DEVICE_OPTIONS BEGIN MAX7000B_ENABLE_VREFB = OFF; MAX7000B_ENABLE_VREFA = OFF; MAX7000B_VCCIO_IOBANK2 = 3.3V; MAX7000B_VCCIO_IOBANK1 = 3.3V; CONFIG_EPROM_PULLUP_RESISTOR = ON; CONFIG_EPROM_USER_CODE = FFFFFFFF; FLEX_CONFIGURATION_EPROM = AUTO; MAX7000AE_ENABLE_JTAG = ON; MAX7000AE_USER_CODE = FFFFFFFF; FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; FLEX6000_ENABLE_JTAG = OFF; CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; MULTIVOLT_IO = OFF; MAX7000S_ENABLE_JTAG = ON; FLEX10K_ENABLE_LOCK_OUTPUT = OFF; MAX7000S_USER_CODE = FFFF; CONFIG_SCHEME_10K = PASSIVE_SERIAL; FLEX10K_JTAG_USER_CODE = 7F; ENABLE_INIT_DONE_OUTPUT = OFF; ENABLE_CHIP_WIDE_OE = OFF; ENABLE_CHIP_WIDE_RESET = OFF; nCEO = UNRESERVED; CLKUSR = UNRESERVED; ADD17 = UNRESERVED; ADD16 = UNRESERVED; ADD15 = UNRESERVED; ADD14 = UNRESERVED; ADD13 = UNRESERVED; ADD0_TO_ADD12 = UNRESERVED; SDOUT = RESERVED_DRIVES_OUT; RDCLK = UNRESERVED; RDYnBUSY = UNRESERVED; nWS_nRS_nCS_CS = UNRESERVED; DATA1_TO_DATA7 = UNRESERVED; DATA0 = RESERVED_TRI_STATED; FLEX8000_ENABLE_JTAG = OFF; CONFIG_SCHEME = ACTIVE_SERIAL; DISABLE_TIME_OUT = OFF; ENABLE_DCLK_OUTPUT = OFF; RELEASE_CLEARS = OFF; AUTO_RESTART = OFF; USER_CLOCK = OFF; SECURITY_BIT = OFF; RESERVED_PINS_PERCENT = 0; RESERVED_LCELLS_PERCENT = 0; END; GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS BEGIN MULTI_LEVEL_SYNTHESIS_MAX9000 = ON; AUTO_IMPLEMENT_IN_EAB = OFF; AUTO_OPEN_DRAIN_PINS = ON; ONE_HOT_STATE_MACHINE_ENCODING = OFF; AUTO_REGISTER_PACKING = OFF; STYLE = NORMAL; AUTO_FAST_IO = OFF; AUTO_GLOBAL_OE = ON; AUTO_GLOBAL_PRESET = ON; AUTO_GLOBAL_CLEAR = ON; AUTO_GLOBAL_CLOCK = ON; MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; OPTIMIZE_FOR_SPEED = 5; DEVICE_FAMILY = FLEX10KE; END; COMPILER_PROCESSING_CONFIGURATION BEGIN USE_QUARTUS_FITTER = OFF; PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; FITTER_SETTINGS = NORMAL; SMART_RECOMPILE = OFF; GENERATE_AHDL_TDO_FILE = OFF; RPT_FILE_USER_ASSIGNMENTS = ON; RPT_FILE_LCELL_INTERCONNECT = ON; RPT_FILE_HIERARCHY = ON; RPT_FILE_EQUATIONS = ON; LINKED_SNF_EXTRACTOR = OFF; OPTIMIZE_TIMING_SNF = OFF; TIMING_SNF_EXTRACTOR = ON; FUNCTIONAL_SNF_EXTRACTOR = OFF; DESIGN_DOCTOR = OFF; DESIGN_DOCTOR_RULES = FLEX; END; COMPILER_INTERFACES_CONFIGURATION BEGIN VHDL_WRITER_VERSION = VHDL87; VHDL_READER_VERSION = VHDL87; SYNOPSYS_MAPPING_EFFORT = MEDIUM; SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; SYNOPSYS_HIERARCHICAL_COMPILATION = ON; SYNOPSYS_DESIGNWARE = OFF; SYNOPSYS_COMPILER = DESIGN; USE_SYNOPSYS_SYNTHESIS = OFF; VHDL_NETLIST_WRITER = OFF; VERILOG_NETLIST_WRITER = OFF; XNF_GENERATE_AHDL_TDX_FILE = ON; XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; EDIF_OUTPUT_VERSION = 200; EDIF_NETLIST_WRITER = OFF; VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; VHDL_TRUNCATE_HIERARCHY_PATH = OFF; EDIF_TRUNCATE_HIERARCHY_PATH = OFF; VERILOG_FLATTEN_BUS = OFF; VHDL_FLATTEN_BUS = OFF; VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; EDIF_INPUT_LMF1 = *.lmf; EDIF_INPUT_LMF2 = *.lmf; EDIF_OUTPUT_EDC_FILE = *.edc; EDIF_INPUT_VCC = VCC; EDIF_INPUT_GND = GND; EDIF_OUTPUT_VCC = VCC; EDIF_OUTPUT_GND = GND; EDIF_INPUT_USE_LMF1 = OFF; EDIF_INPUT_USE_LMF2 = OFF; EDIF_OUTPUT_USE_EDC = OFF; EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; EDIF_FLATTEN_BUS = OFF; EDIF_BUS_DELIMITERS = []; EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; NETLIST_OUTPUT_TIME_SCALE = 0.1ns; END; CUSTOM_DESIGN_DOCTOR_RULES BEGIN MASTER_RESET = OFF; EXPANDER_NETWORKS = ON; RACE_CONDITIONS = ON; DELAY_CHAINS = ON; ASYNCHRONOUS_INPUTS = ON; PRESET_CLEAR_NETWORKS = ON; STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; MULTI_CLOCK_NETWORKS = ON; MULTI_LEVEL_CLOCKS = ON; GATED_CLOCKS = ON; RIPPLE_CLOCKS = ON; END; SIMULATOR_CONFIGURATION BEGIN BIDIR_PIN = STRONG; START_TIME = 0.0ns; GLITCH_TIME = 0.0ns; GLITCH = OFF; OSCILLATION_TIME = 0.0ns; OSCILLATION = OFF; CHECK_OUTPUTS = OFF; SETUP_HOLD = OFF; USE_DEVICE = OFF; SIMULATION_INPUT_FILE = tdspoutfpga6.scf; END_TIME = 1.0us; END; TIMING_ANALYZER_CONFIGURATION BEGIN CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; LIST_PATH_FREQUENCY = 10MHz; LIST_PATH_COUNT = 10; REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; INCLUDE_PATHS_LESS_THAN = OFF; INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; INCLUDE_PATHS_GREATER_THAN = OFF; DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; CELL_WIDTH = 18; LIST_ONLY_LONGEST_PATH = ON; CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; CUT_OFF_IO_PIN_FEEDBACK = ON; AUTO_RECALCULATE = OFF; ANALYSIS_MODE = REGISTERED_PERFORMANCE; END; OTHER_CONFIGURATION BEGIN LAST_MAXPLUS2_VERSION = 9.6; EXPLICIT_FAMILY = 1; ROW_PINS_LCELL_INSERT = ON; CARRY_OUT_PINS_LCELL_INSERT = OFF; NORMAL_LCELL_INSERT = ON; FLEX_10K_52_COLUMNS = 40; DEFAULT_9K_EXP_PER_LCELL = 1/2; LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; LCELLS_PER_ROW_PERCENT = 100; FAN_IN_PER_LCELL_PERCENT = 100; EXP_PER_LCELL_PERCENT = 100; ROW_PINS_PERCENT = 50; ORIGINAL_MAXPLUS2_VERSION = 9.3; COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = ON; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 BEGIN CASCADE_CHAIN = AUTO; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = AUTO; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = OFF; FAST_IO = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 BEGIN CASCADE_CHAIN = MANUAL; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = MANUAL; CARRY_CHAIN_LENGTH = 32; MINIMIZATION = PARTIAL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; IGNORE_SOFT_BUFFERS = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; REGISTER_OPTIMIZATION = OFF; END;