% subckt of dspoutfpga        The DSP expansion port writes to the output fifo %
  
SUBDESIGN   TDSPFIFO     %MODIFIED FROM ORIGINAL DSPFIFO      3/22/00%  %sept 24'00  FIX!!!%

           (XFCLK,         % the expansion port clocks the fifo write port  %
            /XCE2,         % the expansion port write enable to the fifo    %
            XD[31..0],     % the expansion port data to the fifo            %
            /RSTFIFO       % the fifo reset from CNTLSTAT                   %
            :INPUT;
            
            DO[31..0],     % the retimed data to the fifo                   %
            /WEN,          % the retimed write enable to the fifo           %
            WCLK,          % the write clock to the fifo                    %
            /MR            % the reset to the fifo                          %
            :OUTPUT;
            
            CP,            % the local 40 mhs clock                         %
            DMAC,          % the end of DMA frame from the DSP              %
            FIFO_EVTEND    % flag from the readout that an event was read   %
            :INPUT;
            EVENT[7..0],   % the number of events in the fifo       NEW NEW %
            FIFO_EVTRDY    % flag to the readout that an event is available %
            :OUTPUT;)
            
            
       VARIABLE
            
            REG[31..0]       :DFF  ;
            VALID            :DFF  ; %used to retime /XCE AS FIFO'S /WE%
            
            EOW              :DFF  ; %triggered by DMAC of the DSP%
            EOR              :DFF  ; %triggered by EVENTEND from the readout circuit%
            WSYNC[4..1]      :DFF  ; %sync eow to cp%
            RSYNC[4..1]      :DFF  ; %sync eor to cp%
            BLK[7..0]        :DFF  ; %to count how many event block left in the fifo%
            BLKRDY           :DFF  ; %evtrdy flag to fifo read out circuit%
            
            BLKDEC           :LCELL ; %FIX!!!%
            
        BEGIN
         % reset the fifo: %
           REG[].CLRN = /RSTFIFO ;
           VALID.PRN  = /RSTFIFO ;  %new%
           
         % write to the fifo: %
           REG[].CLK = XFCLK  ;
           VALID.CLK = XFCLK  ;
           WCLK      = XFCLK  ;
           
           REG[].D   = XD[]   ;
           VALID.D   = /XCE2  ;     %new%
           
         % output to the fifo: %
           DO[] = REG[]    ;
           /WEN = VALID    ;
           /MR  = /RSTFIFO ;
           
         % the event block control for the fifo read port: %
           EOW.CLK   = DMAC            ;
           EOW.D     = VCC             ;
           EOW.CLRN  = !WSYNC4         ;
           
           WSYNC[].CLK   = CP          ;
           WSYNC[].CLRN  = EOW         ;
           WSYNC1.D      = EOW         ;
           WSYNC[4..2].D = WSYNC[3..1] ;
           
           EOR.CLK   = FIFO_EVTEND     ;
           EOR.D     = VCC             ;
           EOR.CLRN  = !RSYNC4         ;
           
           RSYNC[].CLK   = CP          ;
           RSYNC[].CLRN  = EOR         ;
           RSYNC1.D      = EOR         ;
           RSYNC[4..2].D = RSYNC[3..1] ;
           BLKDEC = RSYNC2 & !RSYNC3 ; %FIX!!!%
           
           BLK[].CLK  = CP             ;
           BLK[].CLRN = /RSTFIFO       ;         %NEW NEW%
           IF     WSYNC3 & %!RSYNC3% !BLKDEC
           THEN   BLK[].D = BLK[] + 1  ;
           ELSIF  
           %RSYNC3 & RSYNC2 & !RSYNC3% BLKDEC & !WSYNC3 & (blk[] !=0) %inhibit blk[] change if blk[]==0%
           THEN   BLK[].D = BLK[] - 1  ;         %happens when a wrong EOR is gen.%  
           ELSE   BLK[].D = BLK[]      ;
           END IF                      ;
           EVENT[]        = BLK[]      ;         %NEW NEW status to VME           %
           
           BLKRDY.CLK  = CP            ;
           BLKRDY.D    = (BLK[]>0)     ;
           FIFO_EVTRDY = BLKRDY & !EOR ;         %NEW NEW !EOR condition added   %
           
           END ;