% subckt of dspoutfpga
  VME writes addressed data to the Dual Port SRAM via the dspinfpga serial port % 

SUBDESIGN   TDPMSERW %modified in add[] increase time, 3/29/00%

              (CP,         % the local 40 mhz clock                 %
              DI[31..0],   % the 32 bit data from VME               %
              WRADD,       % load the dp address from VME           %
              WRDAT        % load and send the data from VME        %
              :INPUT;
              
              DPMBSY,     % the busy to the VME input port          %
              SDH,        % the serialized high order 16 data bits  %
              SDL,        % the serialized low order 16 data bits   %
              SAD,        % the serialized address bits             %
              SFR        % the frame bit writes the data to the DP %
              :OUTPUT;)
             
        VARIABLE
           %   SRF[15..0]        :DFF   ;%
              SRA[15..0]        :DFF   ;
              SRH[15..0]        :DFF   ;
              SRL[15..0]        :DFF   ;
              ADD[15..0]        :DFF   ;
              SEND              :DFF   ;
              CNT[4..0]         :DFF   ;
              
       BEGIN
       
          % load the DP address, inc after sending the frame: %          
             IF    WRADD
             THEN  ADD[].D = DI[15..0] ;
             ELSIF WRDAT                        %new%
             THEN  ADD[].D = ADD[] + 1 ;
             ELSE  ADD[].D = ADD[]     ;
             END IF ;
             
       
          % send the data and address to the Dual Port SRAM: %
             SEND.D = WRDAT # SEND & !(CNT[]==15) ;
             DPMBSY = SEND ;
             
             IF   !SEND
             THEN  CNT[].D = 0         ;
             ELSIF SEND
             THEN  CNT[].D = CNT[] + 1 ;
             ELSE  CNT[].D = CNT[]     ;
             END IF ;
       
             SRL[15..0].D =  WRDAT & DI[15..0]  ;
             SRL[15..1].D = !WRDAT & SRL[14..0] ;
             SDL          =  SRL15 ;
             
             SRH[15..0].D =  WRDAT & DI[31..16] ;
             SRH[15..1].D = !WRDAT & SRH[14..0] ;
             SDH          =  SRH15 ;
             
             SRA[15..0].D =  WRDAT & ADD[15..0] ;
             SRA[15..1].D = !WRDAT & SRA[14..0] ;
             SAD          =  SRA15 ;
             
           %  SRF[0].D     =  WRDAT              ;     %
           %  SRF[15..1].D = !WRDAT & SRF[14..0] ;     %
           %  SFR          =  SRF15 ;                  %
             
              SFR          = WRDAT;             %NEW%
         % clocks: %
             SEND.CLK  = CP ;
             CNT[].CLK = CP ;
             SRL[].CLK = CP ;
             SRH[].CLK = CP ;
             SRA[].CLK = CP ;
            % SRF[].CLK = CP ;%
             ADD[].CLK = CP ;
             
             END ;