% subckt of dspoutfpga         configures the dspinfpga from VME %

SUBDESIGN  TCONFIG  %modified from original config.tdf      3/13/00%

           (CP,
            WRCNF,       % sends the VME data byte serially to the fpga     %
            DI[7..0]     % the VME data byte                                %
           %NSTATUS,%    % nstatus from the fpga to the VME status output   %
           %CONF_DONE%   % conf_done from the fpga to the VME status output %
            :INPUT;
                  
            CNFBSY,     % the busy to the VMEIN port                        %
            DAT0,       % serial data to the fpga                           %
            DCLK        % the serial data clock to the fpga                 %
            :OUTPUT;)
                  
        VARIABLE  
                  SEND             :DFF   ;
                  PH[2..0]         :DFF   ;
                  PHASE            :LCELL ;
                  CNT[2..0]        :DFFE  ;
                  SR[7..0]         :DFFE  ;
                  
         BEGIN 
         
                % send the VME input byte as 8 bits at 5mbits/sec: %
                  SEND.CLK = CP                           ;
                  SEND.D   = WRCNF #
                             SEND & !(PHASE & (CNT[]==7)) ;
                  CNFBSY   = SEND                         ;
                  
                  PH[].CLK = CP              ;
                  PH[].D   = SEND & PH[] + 1 ;
                  PHASE    = (PH[]==7)       ;
                  
                  CNT[].CLK = CP            ;
                  CNT[].ENA = PHASE         ;
                  IF   !SEND
                  THEN  CNT[].D = 0         ;
                  ELSE  CNT[].D = CNT[] + 1 ;
                  END IF;
                  
                  SR[].CLK   = CP                ;
                  SR[].ENA   = PHASE # WRCNF     ;
                  SR[].D     = WRCNF & DI[]      ;
                  SR[6..0].D = !WRCNF & SR[7..1] ;   %lsb shift out first%
                  
                  DAT0 = SR0    ;
                  DCLK = PH[2]  ;
                  
              END ;