% subckt of dspoutfpga            the control register and status flags %  %AUG 15'00%

SUBDESIGN  TCNTLSTAT     %NEW VERSION BASED ON STEPHAN'S PROPOSAL   3/17%
                 (CP,
                  DI[9..0],       % cntl register data from VME  %  
                  WRCNTL,         % VME write to cntl register   %
                  SELSTAT,        % VME read status              %
                  SELCNTL,        %VME READ CONTROL REGISTER     % %NEW%
                  
           % status inputs: %
                  BUFWDCNT[8..0], % number of words in the buffer %
                  DX1_IN,         % DSP FLG DX1 TO INIT INPUT FPGA%
                  SERRDY,         % ready flag from SERR to VME   %
                  BUFFULL,        % buffer full flag              %
                  BUFEF,          % buffer empty flag             %
                  FIFOAF,         % fifo almost full flag to DSP  %
                  FIFOEF,         % fifo empty flag               %
                  FIFOFF,
                  BUSY,           % DSP busy flag to L1 Trigger   %
                  FSX1,         %      %
                  NSTATUS,        % dspinfpga nstatus to VME      %
                  CONF_DONE,      % dspinfpgs conf_done to VME    %
                  SERROVF,        %DSPXMT OVERFLOW FLAG,    NEW   %
                  IRQ1,           %DSPXMT INTERRUPT TO VME, NEW   %
                  EVENT[7..0]     %EVENT COUNT OF FIFO,    NEW NEW%
                  :INPUT;
                  
           % cntl reg flags: %
                  /RSTDSP,       % DSP reset                      %
                  /RSTFIFO,      % Fifo reset                     %
                  /RSTBUF,       % Buffer reset                   %
                  /OFFLINE,      % offline to dspinfpga           %
                  FLAGI1,        % VME flag to DSP                %
                  FLAGI2,        % VME flag to DSP                %
                  NCONFIG        % nconfig from VME to dspinfpga  %
                  :OUTPUT;
                  
           % the status to VME: %
                  DO[31..0]
                  :OUTPUT;)
                  
            VARIABLE
                 REG[9..0]       :DFFE  ;       %STORE VME PARAMETER%
                 
           BEGIN
             % the Processor control register: %
                REG[].CLK = CP        ;
                REG[].ENA = WRCNTL    ;
                REG[].D   = DI[9..0] ;
                
                /RSTDSP    = REG0  ;
                /RSTFIFO   = REG1  ;
                /RSTBUF    = REG2  ;
                /OFFLINE   = REG3  ;
                
                NCONFIG    = REG4  ;
                FLAGI1     = REG5 ;
                FLAGI2     = REG6 ;
                
            % the Processor status: %
                DO[8..0]   = SELSTAT & BUFWDCNT[] ;
                DO9        = SELSTAT & BUFFULL    ;
                DO10       = SELSTAT & BUFEF      ;
                DO11       = SELSTAT & FIFOFF     ;
                DO12       = SELSTAT & FIFOAF     ;
                DO13       = SELSTAT & FIFOEF     ;
                DO14       = SELSTAT & SERRDY     ;
                DO15       = SELSTAT & SERROVF    ; %NEW,DSPSERR OVER FLOW         %
                DO[23..16] = SELSTAT & EVENT[7..0]; %NEW NEW # of events in fifo   %
                DO24       = SELSTAT & BUSY       ; 
                DO25       = SELSTAT & DX1_IN     ;
                DO26       = SELSTAT & FSX1       ;
                DO27       = SELSTAT & IRQ1       ; %NEW,DSPSERR READBACK INTERRUPT%
                DO[29..28] = SELSTAT & gnd        ; % spares                       %
                DO30       = SELSTAT & NSTATUS    ;
                DO31       = SELSTAT & CONF_DONE  ;

              %read the control register%
                DO[9..0]   = SELCNTL & REG[9..0];  %NEW%
                                
               END ;