% SUBCKT OF DSPINFPGA     INITIALIZE THE FPGA                  JUNE 12'00 %

% The INIT to the FPGA, terminates any current FEB frame, resets the TTC fifo,
  resets the Block Counter, and writes 0's to the DP at address 7FFF.

  If the Level1 reset interrupts the DSP, the DSP can process any remaining
  events in the Dual Port, and then send the INIT to the FPGA. %

SUBDESIGN  INITIALIZE

	(CP,
	INIT
	:INPUT;

	INIT_TTC,        % RESET THE TTC FIFO           %
	INIT_FRAME,      % RESET THE FEB FRAME          %
	INIT_BLKCNT,     % RESET THE BLOCK COUNTER      %
	INIT_BLKADD      % WRITE 0'S AT DP ADDRESS 7FFF %
	:OUTPUT;)

	VARIABLE
	REG           :DFF  ;
	SYNC[5..1]    :DFF  ;

	BEGIN
	REG.CLK  = INIT   ;
	REG.D    = VCC    ;
	REG.CLRN = !SYNC3 ;

	SYNC[].CLK    = CP         ;
	SYNC1         = REG        ;
	SYNC[5..2]    = SYNC[4..1] ;

	INIT_TTC      = (SYNC3 & !SYNC4) ;
	INIT_FRAME    = (SYNC3 & !SYNC4) ;
	INIT_BLKCNT   = (SYNC4 & !SYNC5) ;
	INIT_BLKADD   = (SYNC4 & !SYNC5) ;

	END ;