% sub-ckt of dspinfpga                         JUNE 12'00 %

% Transform the FEB serial data to 16 bit parallel data, mask-off 12 data
 ind mux into the data stream during phases 1 to 4 of the 8 serial shift
 phases.
 Shift 2-bit gain data into 16-bit words and mux into the data stream
 during phase 8.
 Output the parallel word even parity.
 Compare the gain for each data word with the corresponding gains of all
 other samples.
 Modified 06/19/2000 by S.Simion: PARITY and PAR_OUT set to 1 for EVEN PARITY %

SUBDESIGN   CHANNEL
	(CP,             % serial input clock     %
	DI_E,            % even input data        %
	DI_O,            % odd  input data        %
	SYNC
	:INPUT;

	ONES_OUT,
	DATA_OUT[11..0],  % data output words        %
	GAIN_OUT[15..0],
	PAR_OUT,          % even parity output       %
	GAIN_ERR          % gain comparison output   %
	:OUTPUT;)

	VARIABLE
	SRE[7..0]       :DFF   ;  % shift register stores even input bits %
	SRO[7..0]       :DFF   ;  % shift register stores ODD  input bits %
	ONES            :LCELL ;  % all ones aligns first input word      %
	PREG[15..0]     :DFFE  ;  % parallel data input register          %
	GAIN[17..0]     :DFFE  ;
	GAIN_COMP       :LCELL ;
	PAR[4..1]       :LCELL ;
	PARITY          :LCELL ;

	BEGIN
% receive serial data: %
	SRE[0].D     = DI_E      ;
	SRE[7..1].D  = SRE[6..0] ;

	SRO[0].D    = DI_O      ;
	SRO[7..1].D = SRO[6..0] ;

% detect all one's: %
	ONES = (SRE[]==255) & (SRO[]==255) ;
	ONES_OUT = ONES                    ;

% convert serial bytes to parallel word %
	PREG[].ENA    = SYNC       ;

	PREG15.D = SRO7 ;  PREG14.D = SRE7 ;
	PREG13.D = SRO6 ;  PREG12.D = SRE6 ;
	PREG11.D = SRO5 ;  PREG10.D = SRE5 ;
	PREG9.D  = SRO4 ;  PREG8.D  = SRE4 ;
	PREG7.D  = SRO3 ;  PREG6.D  = SRE3 ;
	PREG5.D  = SRO2 ;  PREG4.D  = SRE2 ;
	PREG3.D  = SRO1 ;  PREG2.D  = SRE1 ;
	PREG1.D  = SRO0 ;  PREG0.D  = SRE0 ;

% ---------------------------------------------------------------------- %
% shift the gains into an extra word: %
	GAIN[].ENA      = SYNC         ;
	GAIN[17..16].D  = PREG[13..12] ;
	GAIN[15..14].D  = GAIN[17..16] ;
	GAIN[13..12].D  = GAIN[15..14] ;
	GAIN[11..10].D  = GAIN[13..12] ;
	GAIN[9..8].D    = GAIN[11..10] ;
	GAIN[7..6].D    = GAIN[9..8]   ;
	GAIN[5..4].D    = GAIN[7..6]   ;
	GAIN[3..2].D    = GAIN[5..4]   ;
	GAIN[1..0].D    = GAIN[3..2]   ;

% compare the signal gains sample by sample: %
	GAIN_COMP = (PREG[13..12] == GAIN[1..0]) ;
	GAIN_ERR  = !GAIN_COMP                   ;

% check even parity: %
	PAR1 = (PREG0  $ PREG1)  $ (PREG2  $ PREG3)  ;
	PAR2 = (PREG4  $ PREG5)  $ (PREG6  $ PREG7)  ;
	PAR3 = (PREG8  $ PREG9)  $ (PREG10 $ PREG11) ;
	PAR4 = (PREG12 $ PREG13) $ (PREG14 $ PREG15) ;

	PARITY  = (PAR1 $ PAR2) $ (PAR3 $ PAR4) ;
	PAR_OUT = !PARITY ; %%

% data to the next stage: %
	DATA_OUT[11..0] = PREG[11..0]   ;

	GAIN_OUT[15..14] = PREG[13..12] ;
	GAIN_OUT[13..0]  = GAIN[17..4]  ;

% ---------------------------------------------------------------------- %
% CLOCKS: %
	SRE[].CLK     = CP ;
	SRO[].CLK     = CP ;
	PREG[].CLK    = CP ;
	GAIN[].CLK    = CP ;

	END ;