#ifndef _TI_DSP_H
#define _TI_DSP_H
/* ----------------------------------------------------------------------
   Nevis PU board - TMS320C6202
   ---------------------------------------------------------------------- */

/* --- VME address bits 0 to 5 */
typedef enum {
  TI_CONTROL,			/* Control Register (RW) */
  TI_SWRITE,			/* Serial data to McBSP0 (W) */
  TI_DP_ADDR,			/* DP Address Register (W) */ 
  TI_DP_DATA,			/* DP Data Register (W) */
  TI_ALTERA_CONFIG_DATA,	/* Input FPGA Configuration Data (8bit, W) */ 
  TI_STATUS=6,			/* Status Register (R) */
  TI_HIST_DATA,			/* Histogram Fifo Data (R) */ 
  TI_SREAD,			/* Serial data from McBSP0 (R) */
  TI_RESET			/* Controller Reset (W, dataless function) */
} ti_addr_t;

typedef enum {
  TI_AUTO,
  TI_REBOOT
} ti_bootMode;

/* --- Control Register masks */
#define CW_nRSTDSP        0x01	/* DSP RESET */
#define CW_nRSTFIFO       0x02	/* Event FIFO RESET */
#define CW_nRSTBUF        0x04	/* Histogram FIFO RESET */
#define CW_OFFLINE        0x08	/* Offline pin to Input FPGA */
#define CW_nCONFIG        0x10	/* nCONFIG pin to Input FPGA */ 
#define CW_FLG1           0x20
#define CW_FLG2           0x40

/* --- Status Register masks */
#define TI_STATUS_BWC     0x000001ff
#define TI_STATUS_BFF     0x00000200
#define TI_STATUS_BEF	  0x00000400
#define TI_STATUS_FIFOFF  0x00000800
#define TI_STATUS_FIFOAF  0x00001000
#define TI_STATUS_FIFOEF  0x00002000
#define TI_STATUS_SRDY    0x00004000
#define TI_STATUS_SOVF    0x00008000
#define TI_STATUS_NEVT    0x00ff0000
#define TI_STATUS_BUSY    0x01000000
#define TI_STATUS_DX1     0x02000000
#define TI_STATUS_FSX1    0x04000000
#define TI_nSTATUS	  0x40000000
#define TI_CONF_DONE	  0x80000000

/* --- Output FPGA addresses */
#define ADD_MODE	0x8000	/* accepts D0 */
#define ADD_NSAMP	0x9000	/* accepts D0..D6 */
#define ADD_NGAIN	0xa000	/* accepts D0..D2 */
#define ADD_MAP		0xb000	/* accepts D0..D8 */
#define ADD_SHFT        0xc000  /* accepts D0..D2 */

/* --- PU descriptor - will be extended */
typedef struct {
  int rodid;
  int puid;
  unsigned int controlWord;    /* - filled automatically at initialization */
  int nsamp;                   /* Number of samples for input FPGA */
  int ngain;                   /* Number of gains for input FPGA */
  const char *bootFile;        /* DSP code in Tektronix format */
  const char *calibrationFile; /* Calibration constants in Tektronix format */
} ti_dsp_t, *ti_dsp_p;

/* --- VME access function prototyes */
void vme_dsp_write(ti_dsp_p, ti_addr_t, unsigned int);
int  vme_dsp_read (ti_dsp_p, ti_addr_t);
void vme_dsp_writeblk(ti_dsp_p, ti_addr_t, int, unsigned int *);
void vme_dsp_readblk (ti_dsp_p, ti_addr_t, int, unsigned int *);

#define ti_writeCW(x) vme_dsp_write(x, TI_CONTROL, (x)->controlWord)
#define ti_syscall(x, y) vme_dsp_write(x, TI_SWRITE, y)
#define ti_status(x) vme_dsp_read(x, TI_STATUS)

/* --- Library function prototypes */
void ti_dpcpy(ti_dsp_p dsp, unsigned int s1, unsigned int *s2, int wc);
void ti_dpset(ti_dsp_p dsp, unsigned int s, unsigned int word, int wc);
int  ti_dpsend_xfile(ti_dsp_p dsp, const char *file);
int  ti_hread(ti_dsp_p dsp, unsigned int *buf, int wc);
void ti_hprnt(ti_dsp_p dsp);
int  ti_hreadblk(ti_dsp_p dsp, unsigned int *buf, int wc);
void ti_boot(ti_dsp_p dsp, ti_bootMode);
int  ti_altera_cfg(ti_dsp_p dsp, ti_bootMode);
void ti_pstatus  (unsigned int status);
void ti_psstatus (unsigned int status);
int  ti_fpstatus (ti_dsp_p dsp);
int  ti_fpsstatus(ti_dsp_p dsp);
void ti_interrupt(ti_dsp_p dsp);
#ifdef __GNUC__
#define fpga_map_ fpga_map__
#endif
void fpga_map_(int *nsamp, int *ngain, unsigned int *map);

#endif /* _TI_DSP_H */