#include #include "ti_dsp.h" /* ---------------------------------------------------------------------- Boots the PU board specified bu the dsp descriptor. The input FPGA is configured from file ALTERA.dat. The DSP code is taken from file xfile0, while the calibration constants are taken from file xfile1. This routine does not actually distinguish between different types of .x0 files. S.Simion Nov/2000 ---------------------------------------------------------------------- */ void ti_boot(ti_dsp_p dsp, ti_bootMode bootMode) { int ist; fprintf(stderr, "ti_boot: Booting rodid=%d puid=%d\n", dsp->rodid, dsp->puid); /* -- Get local copy of the PU control word */ dsp->controlWord = vme_dsp_read(dsp, TI_CONTROL); vme_check(); fprintf(stderr, "ti_boot: PU Control Word = 0x%x\n", dsp->controlWord); /* -- The input FPGA must first go offline */ if ((dsp->controlWord & CW_OFFLINE) == 0){ dsp->controlWord |= CW_OFFLINE; ti_writeCW(dsp); } /* ==================== PHASE 0 : Load the ALTERA ==================== */ /* -- Reset the DSP and the FIFOs */ fputs("ti_boot: DSP reset and hold\n", stderr); dsp->controlWord &= ~(CW_nRSTDSP | CW_nRSTFIFO | CW_nRSTBUF); ti_writeCW(dsp); usleep(1000); /* -- Load input FPGA */ fputs("ti_boot: Loading input FPGA\n", stderr); ist = ti_altera_cfg(dsp, bootMode); if (ist) exit(1); /* -- Load parameters for input FPGA */ fputs("ti_boot: Loading parameters for input FPGA\n", stderr); { unsigned int *map = (unsigned int *) calloc(512, sizeof(int)); fpga_map_(&dsp->nsamp, &dsp->ngain, map); ti_dpset(dsp, ADD_MODE, 1, 1); /* MAP Mode is enabled */ ti_dpset(dsp, ADD_NSAMP, dsp->nsamp, 1); ti_dpset(dsp, ADD_NGAIN, dsp->ngain, 1); ti_dpcpy(dsp, ADD_MAP, map, 512); ti_dpset(dsp, ADD_SHFT, 0, 1); free(map); } /* ==================== PHASE 1 : Load DSP code ==================== */ /* -- Load DSP code */ if (dsp->bootFile != NULL) ist = ti_dpsend_xfile(dsp, dsp->bootFile); /* -- Load the calibration constants at address 10000h */ if (dsp->calibrationFile != NULL) ist = ti_dpsend_xfile(dsp, dsp->calibrationFile); /* ==================== PHASE 2 : Reset the DSP ==================== */ /* Reset the DSP who will wait for an interrupt before it starts polling on the event counters */ fputs("ti_boot: Sending RESET pulse to DSP\n", stderr); dsp->controlWord |= (CW_nRSTDSP | CW_nRSTFIFO); ti_writeCW(dsp); /* The DSP copies the code from the dual-port RAM and runs cinit() */ usleep(5000); ist = ti_status(dsp); if (ist & TI_STATUS_SRDY){ ist = vme_dsp_read(dsp, TI_SREAD); fprintf(stderr, "ti_boot: DSP serial data=0x%x\n", ist); } else fputs("ti_boot: No DSP serial data\n", stderr); /* -- Re-initialize full RAM */ fputs("ti_boot: Reinitialize full dual-port RAM\n", stderr); ti_dpset(dsp, 0, 0, 32768); vme_check(); #ifdef VERBOSE ti_fpstatus(dsp); #endif /* -- Enable FIFO access and switch the input FPGA to online mode */ fputs("ti_boot: Enable FIFO access. Input FPGA online mode.\n", stderr); dsp->controlWord |= (CW_nRSTFIFO | CW_nRSTBUF); dsp->controlWord &= ~CW_OFFLINE; ti_writeCW(dsp); #ifdef VERBOSE ti_fpstatus(dsp); #endif /* -- Send INT7 i.e. start event processing */ fputs("ti_boot: Sending INT7 to start event processing\n", stderr); ti_interrupt(dsp); ist = ti_status(dsp); if (ist & TI_STATUS_SRDY){ ist = vme_dsp_read(dsp, TI_SREAD); fprintf(stderr, "ti_boot: DSP serial data=0x%x\n", ist); } else fputs("ti_boot: No DSP serial data\n", stderr); fputs("ti_boot: Initialization complete\n", stderr); }