;; Send an event to the output FIFO.
	;; This routine will block until the transfer is finished.
	;; Note that synchronization is enabled, and the transfer will
	;; not proceed if the output FIFO is almost full.
	;; In this case, we can either return immediately EWOULDBLOCK
	;; or wait here until the data can be written.
	;; You should not attempt to transfer more than 1024 words in
	;; one go, because only a single-frame DMA is implemented here.
	;;
	;; Input arguments:
	;; - data pointer
	;; - number of words
	;; - flag: if nonzero, then don't block on FIFO almost full.
	;;
	;; S.Simion / Nevis DSP 6202 / 11-Sep-2000
	;;
_sendEvt:
	MVC	IFR, B0
||	MV	A6, B1		; flag (3rd argument)
||	MVKL	0x01840004, A0	; address of the DMA2 primary control register

   [B1]	EXT	B0, 25, 31, B1	; interested in IF6 = FIFO almost full
||	MVKH	0x01840004, A0

  [!B1]	STW	A4, *+A0[4]	; load the source address (1st argument)
||	MVKL	0x70000000, A1
|| [B1]	B	B3		; return->

  [!B1]	STW	B4, *+A0[8]	; load the word count (2nd argument)
||	MVKL	0x003c0008, B2
||	MVKH	0x70000000, A1

  [!B1]	STW	A1, *+A0[6]	; load the destination address
||	MVKL	0x06018011, A1
||	MVKH	0x003c0008, B2

  [!B1]	STW	B2, *+A0[2]	; load the secondary control register
||	MVKH	0x06018011, A1

  [!B1]	STW	A1, *A0		; load the primary control register and GO
||[!B1]	ZERO	A4		; prepare to return 0

wait:
	MVC	IFR, B0
|| [B1]	MVK	11, A4		; -> return EWOULDBLOCK

	EXT	B0, 20, 31, B0	; interested in IF11 = DMAC2
   [B0]	B	B3		; return->
  [!B0]	B	wait
	NOP	5
	.global	_sendEvt