.global	_periph_init

_periph_init:	.cproc
	MVKL	0x01800000, A4	; EMIF base
	MVKH	0x01800000, A4
	MVKL	0xfff10220, A5	; Read Setup=1 Strobe=2 Hold=0 (was Hold=1)
	MVKH	0xfff10220, A5
	STW	A5, *+A4[1]	; configuring EMIF CE1 space control
	MVKL	0x01880000, A4	; Expansion Bus Global Control (XBGC) register
	MVKH	0x01880000, A4
*	MVK	0x7000,	A5	; Clock = CPU/2
	MVK	0x6000,	A5	; Clock = CPU/4
*	MVK	0x5000, A5	; Clock = CPU/6
*	MVK	0x4000, A5	; Clock = CPU/8
	STW	A5, *A4
	MVKL	0x018c0000, A4	; Serial port channel 0 base
	MVKH	0x018c0000, A4
	MVKL	0x000100A0, A5
	MVKH	0x000100A0, A5
	STW	A5, *+A4[3]	; McBSP0 RCR (Receive control register)
	STW	A5, *+A4[4]	; McBSP0 XCR (Transmit control register)
	MVKL	0x20200008, A5
	MVKH	0x20200008, A5
	STW	A5, *+A4[5]	; McBSP0 SRGR (Sample rate generator register)
	MVK	0x00000A02, A5
	STW	A5, *+A4[9]	; McBSP0 PCR (Pin control register)
	MVKL	0x00C10001, A5
	MVKH	0x00C10001, A5
	STW	A5, *+A4[2]	; McBSP0 SPCR (Serial port control register)
	MVKL	0xdeadbeef, A5
	MVKH	0xdeadbeef, A5
	STW	A5, *+A4[1]	; Send a message to the serial port (DXR)

	;; McBSP1 PCR Configuration
	;; Receiver and transmitter are general-purpose outputs (RIOEN=XIOEN=1)
	;; DX1 is always output driven by DX_STAT
	;; We send a DX1 pulse to initialize the input FPGA
	;; FSXM=1 selects FSX1 as output driven by FSXP
	MVKL	0x01900000, A4	; McBSP1 base address
	MVKH	0x01900000, A4
	MVK     0x3000, A5	; DX_STAT=0
	STW     A5, *+A4[9]
	MVK	0x3020, A5	; DX_STAT=1
	STW	A5, *+A4[9]
	MVK	0x3800, A5	; DX_STAT=0 FSXM=1 FSXP=0
	STW	A5, *+A4[9]	; McBSP1 PCR

	MVKL	0x019c0000, A4	; Interrupt multiplexer high
	MVKH	0x019c0000, A4
	MVKL	0x08202d4d, A5	; RINT0 replaces SD_INT as INT10
	MVKH	0x08202d4d, A5
	STW	A5, *A4
	.return
	.endproc