;****************************************************************************** ;* TMS320C6x ANSI C Codegen Version 4.00 * ;* Date/Time created: Sun Feb 4 14:02:03 2001 * ;****************************************************************************** ;****************************************************************************** ;* GLOBAL FILE PARAMETERS * ;* * ;* Architecture : TMS320C620x * ;* Optimization : Disabled * ;* Optimizing for : Compile time, Ease of Development * ;* Based on options: no -o, no -ms * ;* Endian : Little * ;* Interrupt Thrshld : Disabled * ;* Memory Model : Small * ;* Calls to RTS : Near * ;* Pipelining : Disabled * ;* Memory Aliases : Presume are aliases (pessimistic) * ;* Debug Info : No Debug Info * ;* * ;****************************************************************************** FP .set A15 DP .set B14 SP .set B15 .global $bss .global _periph_init .sect ".text" ;****************************************************************************** ;* FUNCTION NAME: _periph_init * ;* * ;* Regs Modified : A4,A5 * ;* Regs Used : A4,A5,B3 * ;****************************************************************************** _periph_init: ;** --------------------------------------------------------------------------* ; ; _periph_init: .cproc MVKL .S1 0xfff10220,A5 ; |6| Read Setup=1 Strobe=2 Hold=0 (was Hold=1) MVKL .S1 0x1800000,A4 ; |4| EMIF base MVKH .S1 0xfff10220,A5 ; |7| MVKH .S1 0x1800000,A4 ; |5| MVKL .S1 0x1880000,A4 ; |9| Expansion Bus Global Control (XBGC) register || STW .D1T1 A5,*+A4(4) ; |8| configuring EMIF CE1 space control MVK .S1 0x6000,A5 ; |12| Clock = CPU/4 MVKH .S1 0x1880000,A4 ; |10| MVKL .S1 0x100a0,A5 ; |18| || STW .D1T1 A5,*A4 ; |15| MVKL .S1 0x18c0000,A4 ; |16| Serial port channel 0 base MVKH .S1 0x100a0,A5 ; |19| MVKH .S1 0x18c0000,A4 ; |17| STW .D1T1 A5,*+A4(12) ; |20| McBSP0 RCR (Receive control register) MVKL .S1 0x20200008,A5 ; |22| || STW .D1T1 A5,*+A4(16) ; |21| McBSP0 XCR (Transmit control register) MVKH .S1 0x20200008,A5 ; |23| MVK .S1 0xa02,A5 ; |25| || STW .D1T1 A5,*+A4(20) ; |24| McBSP0 SRGR (Sample rate generator register) MVKL .S1 0xc10001,A5 ; |27| || STW .D1T1 A5,*+A4(36) ; |26| McBSP0 PCR (Pin control register) MVKH .S1 0xc10001,A5 ; |28| MVKL .S1 0xdeadbeef,A5 ; |30| || STW .D1T1 A5,*+A4(8) ; |29| McBSP0 SPCR (Serial port control register) MVKH .S1 0xdeadbeef,A5 ; |31| MVKL .S1 0x1900000,A4 ; |39| McBSP1 base address || STW .D1T1 A5,*+A4(4) ; |32| Send a message to the serial port (DXR) MVKH .S1 0x1900000,A4 ; |40| MVK .S1 0x3020,A5 ; |41| DX_STAT=1 B .S2 B3 || MVK .S1 0x3800,A5 ; |43| DX_STAT=0 FSXM=1 FSXP=0 || STW .D1T1 A5,*+A4(36) ; |42| McBSP1 PCR MVKL .S1 0x19c0000,A4 ; |46| Interrupt multiplexer high || STW .D1T1 A5,*+A4(36) ; |44| McBSP1 PCR MVKL .S1 0x8202d4d,A5 ; |48| RINT0 replaces SD_INT as INT10 MVKH .S1 0x19c0000,A4 ; |47| MVKH .S1 0x8202d4d,A5 ; |49| STW .D1T1 A5,*A4 ; |50| ; BRANCH OCCURS ; .endproc