! / 0 0 0 0 66 ` ††Ò’_memcpy_dma_memcpy_xce3_pause_periph_initmemcpy_dma.obj/ 968644042 0 0 0 527 ` Â9¼UÊF ™.text ¦ .data@.bss€(€h€t w‚ (€u i€©€tBŒtŒdŒ`ž‡€dŒ€`b €(€(€h€h€tBŒw (€i¸t‚ ©€tÂŒtŒdŒ`ž‡€dŒ€`b €ÿþg.text .data.bssL'baavWaqVD_memcpy_dma_memcpy_xce3 pause.obj/ 968644042 0 0 0 388 ` Â9¼UÊæ™.text@¦ .data@.bss€â„R¢¢” b ∠*@€¢Œÿþg.text@.data.bss_pausebaa94a4VDperiph_init.obj/968644044 0 0 0 497 ` Â9¼UËF™.text ¦ .data@.bss€((èøÿhÀ)t"(°hÄ)P€t(è€hÆtb)€t‚h)…t¢©€t"‘é`€c ©wßtBèVï)t"hÈ(œt"‘ÿþg.text .data.bssbaaiaaGWD_periph_init memcpy_dma.sa/ 968626346 0 0 0 1161 ` .global _memcpy_dma .global _memcpy_xce3 _memcpy_dma: .cproc s1, s2, wc * MVKL 0x01840040, A3 ; address of the DMA1 primary control register * MVKH 0x01840040, A3 MVKL 0x01840004, A3 ; address of the DMA2 primary control register MVKH 0x01840004, A3 MVKL 0x00040008, A1 MVKH 0x00040008, A1 STW A1, *+A3[2] ; secondary control register STW s1, *+A3[6] ; destination address (1st argument) STW s2, *+A3[4] ; source address (2nd argument) STW wc, *+A3[8] ; word count (3rd argument) MVK 0x11, A1 STW A1, *A3 ; trigger the transfer wait: LDW *A3, A1 EXTU A1, 28, 30, A1 NOP 5 [A1] B wait .return .endproc _memcpy_xce3: .cproc s2, wc MVKL 0x01840004, A3 ; address of the DMA2 primary control register MVKH 0x01840004, A3 MVKL 0x00040008, A1 MVKH 0x00040008, A1 STW A1, *+A3[2] ; secondary control register MVKL 0x70000000, A1 ; destination address = XCE3 MVKH 0x70000000, A1 STW A1, *+A3[6] ; destination address STW s2, *+A3[4] ; source address (1st argument) STW wc, *+A3[8] ; word count (2nd argument) MVK 0x11, A1 STW A1, *A3 ; trigger the transfer wait: LDW *A3, A1 EXTU A1, 28, 30, A1 NOP 5 [A1] B wait .return .endproc pause.sa/ 968626480 0 0 0 598 ` .global _pause _pause: ;; This routine does not actually enable interrupts. ;; The CPU goes to power-down mode PD1. Wake-up from PD1 is ;; triggered by a non-enabled interrupt, normally INT7. ;; Execution continues without need for an interrupt service packet. ;; See Instruction Set Reference page XXX. B Next MVC CSR,B5 ; copy control status register ADDK 0x4400,B5 ; select PD1 wake by non-enabled interrupt MVC B5,CSR ; enter PD1 NOP NOP Next: NOP NOP 6 B B3 ; return to caller MVC IFR,B5 MV B5,A4 ; return value is IFR register MVK 0x80,B3 MVC B3,ICR ; clear INT7 NOP periph_init.sa/ 968641924 0 0 0 947 ` .global _periph_init _periph_init: .cproc MVKL 0x01800000, A4 ; EMIF CE1 MVKH 0x01800000, A4 MVKL 0xfff10220, A5 ; Read Setup=1 Strobe=2 Hold=0 (was Hold=1) MVKH 0xfff10220, A5 STW A5, *+A4[1] MVKL 0x01880000, A4 ; Expansion Bus global control register MVKH 0x01880000, A4 * MVK 0x7000, A5 ; Clock = CPU/2 MVK 0x6000, A5 ; Clock = CPU/4 * MVK 0x5000, A5 ; Clock = CPU/6 * MVK 0x4000, A5 ; Clock = CPU/8 STW A5, *A4 MVKL 0x018c0000, A4 ; Serial port channel 0 MVKH 0x018c0000, A4 MVKL 0x000100A0, A5 MVKH 0x000100A0, A5 STW A5, *+A4[3] STW A5, *+A4[4] MVKL 0x20200008, A5 MVKH 0x20200008, A5 STW A5, *+A4[5] MVK 0x00000A02, A5 STW A5, *+A4[9] MVKL 0x00C10001, A5 MVKH 0x00C10001, A5 STW A5, *+A4[2] MVKL 0xdeadbeef, A5 MVKH 0xdeadbeef, A5 STW A5, *+A4[1] ; Send a message to the serial port MVKL 0x01900000, A4 ; Serial port channel 1 (FSX1) MVKH 0x01900000, A4 MVK 0x3800, A5 STW A5, *+A4[9] .return .endproc