TMS320C6x COFF Assembler         Version 4.00     Mon Jun 25 22:04:33 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
ppu.asm                                                              PAGE    1

       1          00000004  src     .set    A4
       2          00000024  dst     .set    B4
       3                    
       4          00000006  S0      .set    A6
       5          00000007  S1      .set    A7
       6          00000026  T0      .set    B6
       7          00000027  T1      .set    B7
       8                    
       9          00000002  x       .set    A2
      10          00000022  y       .set    B2
      11                    
      12                            
      13                    ppu2    .macro  
      14                            LDW     *src++, x
      15                    ||      STW     B0, *dst++
      16                    ||      ADDU    B0, S1:S0, S1:S0
      17                    || [A1] NOT     A0, A0
      18                    ||      SHL     y, 1, B1:B0
      19                    
      20                            LDW     *src++, y
      21                    ||      STW     A0, *dst++
      22                    ||      SHL     x, 1, A1:A0
      23                    ||      ADDU    A0, T1:T0, T1:T0
      24                    || [B1] NOT     B0, B0
      25                            .endm
      26                    
      27 00000000                   ppu2
1        00000000 01103665          LDW     *src++, x
1        00000004 001036F7  ||      STW     B0, *dst++
1        00000008 03181539  ||      ADDU    B0, S1:S0, S1:S0
1        0000000c 8003E2A1  || [A1] NOT     A0, A0
1        00000010 000824A2  ||      SHL     y, 1, B1:B0
1                           
1        00000020 01103667          LDW     *src++, y
1        00000024 001036F5  ||      STW     A0, *dst++
1        00000028 000824A1  ||      SHL     x, 1, A1:A0
1        0000002c 0318153B  ||      ADDU    A0, T1:T0, T1:T0
1        00000030 4003E2A2  || [B1] NOT     B0, B0
      28 00000034                   ppu2
1        00000040 01103665          LDW     *src++, x
1        00000044 001036F7  ||      STW     B0, *dst++
1        00000048 03181539  ||      ADDU    B0, S1:S0, S1:S0
1        0000004c 8003E2A1  || [A1] NOT     A0, A0
1        00000050 000824A2  ||      SHL     y, 1, B1:B0
1                           
1        00000060 01103667          LDW     *src++, y
1        00000064 001036F5  ||      STW     A0, *dst++
1        00000068 000824A1  ||      SHL     x, 1, A1:A0
1        0000006c 0318153B  ||      ADDU    A0, T1:T0, T1:T0
1        00000070 4003E2A2  || [B1] NOT     B0, B0
      29 00000074                   ppu2
1        00000080 01103665          LDW     *src++, x
1        00000084 001036F7  ||      STW     B0, *dst++
1        00000088 03181539  ||      ADDU    B0, S1:S0, S1:S0
1        0000008c 8003E2A1  || [A1] NOT     A0, A0
TMS320C6x COFF Assembler         Version 4.00     Mon Jun 25 22:04:33 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
ppu.asm                                                              PAGE    2

1        00000090 000824A2  ||      SHL     y, 1, B1:B0
1                           
1        000000a0 01103667          LDW     *src++, y
1        000000a4 001036F5  ||      STW     A0, *dst++
1        000000a8 000824A1  ||      SHL     x, 1, A1:A0
1        000000ac 0318153B  ||      ADDU    A0, T1:T0, T1:T0
1        000000b0 4003E2A2  || [B1] NOT     B0, B0
      30 000000b4                   ppu2
1        000000c0 01103665          LDW     *src++, x
1        000000c4 001036F7  ||      STW     B0, *dst++
1        000000c8 03181539  ||      ADDU    B0, S1:S0, S1:S0
1        000000cc 8003E2A1  || [A1] NOT     A0, A0
1        000000d0 000824A2  ||      SHL     y, 1, B1:B0
1                           
1        000000e0 01103667          LDW     *src++, y
1        000000e4 001036F5  ||      STW     A0, *dst++
1        000000e8 000824A1  ||      SHL     x, 1, A1:A0
1        000000ec 0318153B  ||      ADDU    A0, T1:T0, T1:T0
1        000000f0 4003E2A2  || [B1] NOT     B0, B0
      31                            

 No Errors, No Warnings