;****************************************************************************** ;* TMS320C6x ANSI C Codegen Version 4.00 * ;* Date/Time created: Wed Jun 20 09:26:58 2001 * ;****************************************************************************** ;****************************************************************************** ;* GLOBAL FILE PARAMETERS * ;* * ;* Architecture : TMS320C620x * ;* Optimization : Enabled at level 3 * ;* Optimizing for : Speed * ;* Based on options: -o3, no -ms * ;* Endian : Little * ;* Interrupt Thrshld : Disabled * ;* Memory Model : Small * ;* Calls to RTS : Near * ;* Pipelining : Enabled * ;* Speculative Load : Enabled (Threshold = 12 ) * ;* Memory Aliases : Presume not aliases (optimistic) * ;* Debug Info : No Debug Info * ;* * ;****************************************************************************** FP .set A15 DP .set B14 SP .set B15 .global $bss ; opt6x -t -v6200 -O3 /var/tmp/aaapUaG45 /var/tmp/daasUaG45 .sect ".text" .global _ldc_ ;****************************************************************************** ;* FUNCTION NAME: _ldc_ * ;* * ;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,B0,B1,B2, * ;* B4,B5,B6,B7,B8,B9,SP * ;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,B0,B1,B2, * ;* B3,B4,B5,B6,B7,B8,B9,SP * ;* Local Frame Size : 0 Args + 0 Auto + 12 Save = 12 byte * ;****************************************************************************** _ldc_: ;** --------------------------------------------------------------------------* STW .D2T1 A12,*SP--(16) ; |5| STW .D2T1 A11,*+SP(12) ; |5| || MVK .S1 0xffffffff,A9 ; |6| || ZERO .L2 B8 ; |9| ZERO .D1 A10 ; |8| || MVK .S1 0x20,A11 ; |10| || STW .D2T1 A10,*+SP(8) ; |5| || MV .L1X B4,A12 ; || MV .L2X A4,B9 ; || MVK .S2 0x4,B7 ; |15| ;*----------------------------------------------------------------------------* ;* SOFTWARE PIPELINE INFORMATION ;* ;* Known Minimum Trip Count : 32 ;* Known Maximum Trip Count : 32 ;* Known Max Trip Count Factor : 32 ;* Loop Carried Dependency Bound(^) : 0 ;* Unpartitioned Resource Bound : 2 ;* Partitioned Resource Bound(*) : 2 ;* Resource Partition: ;* A-side B-side ;* .L units 1 1 ;* .S units 1 1 ;* .D units 1 1 ;* .M units 0 0 ;* .X cross paths 0 1 ;* .T address paths 2* 0 ;* Long read paths 1 0 ;* Long write paths 0 0 ;* Logical ops (.LS) 0 0 (.L or .S unit) ;* Addition ops (.LSD) 3 1 (.L or .S or .D unit) ;* Bound(.L .S .LS) 1 1 ;* Bound(.L .S .D .LS .LSD) 2* 2* ;* ;* Searching for software pipeline schedule at ... ;* ii = 2 Register is live too long ;* ii = 2 Register is live too long ;* ii = 2 Register is live too long ;* ii = 3 Schedule found with 4 iterations in parallel ;* done ;* ;* Collapsed epilog stages : 3 ;* Prolog not entirely removed ;* Collapsed prolog stages : 2 ;* ;* Minimum required memory pad : 12 bytes ;* ;* Minimum safe trip count : 1 ;*----------------------------------------------------------------------------* L1: ; PIPED LOOP PROLOG MV .L1X B9,A4 ; || B .S2 L2 ; (P) |28| LDW .D1T1 *A4++,A3 ; (P) |24| MV .L2 B9,B4 ; || ZERO .L1 A6 ; |21| || MVK .S1 0x2,A1 ; init prolog collapse predicate || MVK .S2 0x20,B1 ; |23| ;** --------------------------------------------------------------------------* L2: ; PIPED LOOP KERNEL MV .L1 A7,A5 ; |24| || [ B0] ADD .S1 1,A7,A0 ; |25| || [ B1] B .S2 L2 ; @|28| [ B0] ABS .L1 A0,A5 ; |25| || SHL .S1 A3,1,A7 ; @|24| || LDW .D1T1 *A4++,A3 ; @@@|24| [ A1] SUB .L1 A1,1,A1 ; || [!A1] ADD .S1 A5,A6,A6 ; |27| || [!A1] STW .D2T1 A5,*B4++ ; |26| || CMPLT .L2X A7,0,B0 ; @|25| || [ B1] SUB .S2 B1,1,B1 ; @@|28| ;*----------------------------------------------------------------------------* ;* SOFTWARE PIPELINE INFORMATION ;* ;* Known Minimum Trip Count : 32 ;* Known Maximum Trip Count : 32 ;* Known Max Trip Count Factor : 32 ;* Loop Carried Dependency Bound(^) : 9 ;* Unpartitioned Resource Bound : 5 ;* Partitioned Resource Bound(*) : 6 ;* Resource Partition: ;* A-side B-side ;* .L units 0 2 ;* .S units 5 1 ;* .D units 2 2 ;* .M units 0 0 ;* .X cross paths 1 5 ;* .T address paths 4 0 ;* Long read paths 2 0 ;* Long write paths 0 0 ;* Logical ops (.LS) 5 3 (.L or .S unit) ;* Addition ops (.LSD) 4 6 (.L or .S or .D unit) ;* Bound(.L .S .LS) 5 3 ;* Bound(.L .S .D .LS .LSD) 6* 5 ;* ;* Searching for software pipeline schedule at ... ;* ii = 9 Register is live too long ;* ii = 9 Register is live too long ;* ii = 9 Register is live too long ;* ii = 10 Register is live too long ;* ii = 10 Register is live too long ;* ii = 10 Register is live too long ;* ii = 11 Schedule found with 3 iterations in parallel ;* done ;* ;* Epilog not entirely removed ;* Collapsed epilog stages : 1 ;* ;* Prolog not removed ;* Collapsed prolog stages : 0 ;* ;* Minimum required memory pad : 4 bytes ;* ;* Minimum safe trip count : 2 ;*----------------------------------------------------------------------------* L3: ; PIPED LOOP EPILOG AND PROLOG MVK .S2 1,B6 ; |51| || SUB .D1 A11,5,A11 ; || CMPLT .L2X A11,5,B0 ; || MVK .S1 25,A0 ; |31| || LMBD .L1 1,A6,A5 ; |31| MVK .S1 31,A1 ; || [ B0] ADD .L2 1,B8,B8 ; |43| || SUB .L1X B9,4,A2 ; |52| MVC .S2 CSR,B8 || MV .L2 B8,B4 AND .L2 -2,B8,B5 || [ B0] ADDK .S1 32,A11 ; |44| || [ B0] NEG .L1 A11,A0 ; |42| || SUB .D1 A0,A5,A3 ; |31| MV .L1 A11,A6 || ADD .S1 1,A3,A5 ; |39| [ B0] SHRU .S1 A5,A0,A4 ; |42| SHL .S1 A5,A11,A4 ; |47| || [ B0] OR .L1 A4,A10,A10 ; |42| SHL .S1X B6,A3,A0 ; |51| || MVC .S2 B5,CSR ; interrupts off || [ B0] ZERO .L1 A10 ; |45| || [ B0] STW .D1T1 A10,*A12++ ; |43| ADD .S1 A9,A0,A8 ; |52| || MV .L2X A12,B5 || OR .L1 A4,A10,A10 ; |47| || LDW .D1T1 *++A2,A4 ; (P) ^ |62| MV .L2X A10,B6 NOP 3 SHRU .S1 A4,A3,A7 ; (P) ^ |62| SUB .L1 A6,A7,A5 ; (P) ^ |62| CMPLT .L2X A5,0,B0 ; (P) ^ |62| [ B0] ADD .L2 1,B4,B4 ; (P) |64| || [ B0] LDW .D1T1 *A2,A4 ; (P) ^ |65| || [ B0] ADDK .S1 32,A5 ; (P) |65| MV .L2 B0,B2 ; (P) Inserted to split a long life || SUB .L1 A5,A3,A5 ; (P) |75| || LDW .D1T1 *++A2,A4 ; (P) @ ^ |62| ;** --------------------------------------------------------------------------* L4: ; PIPED LOOP KERNEL [ B2] STW .D2T1 A10,*B5++ ; |64| ADD .S1 A9,A5,A5 ; |75| NEG .S1 A5,A7 ; |77| AND .L1 A8,A4,A6 ; ^ |74| || CMPLT .L2X A5,0,B1 ; |75| [ A1] SUB .D1 A1,1,A1 ; |84| || [ B1] ADD .L2 1,B4,B4 ; |78| || [ B1] ADDK .S1 32,A5 ; |79| || OR .L1 A0,A6,A6 ; |74| || MV .S2 B1,B0 ; Inserted to split a long life [ B2] ZERO .L1 A10 ; |66| || [ A1] B .S2 L4 ; |84| || SHRU .S1 A6,A7,A7 ; |77| [ B2] MV .L2X A10,B6 ; Define a twin register || [ B1] OR .L1 A7,A10,A10 ; |77| || SHRU .S1 A4,A3,A7 ; @ ^ |62| [ B0] STW .D2T1 A10,*B5++ ; |78| || SHL .S1 A6,A5,A6 ; |82| || [ B0] MV .L2X A10,B6 ; Define a twin register || SUB .L1 A5,A7,A5 ; @ ^ |62| [ B0] ZERO .S2 B6 ; |80| || CMPLT .L2X A5,0,B0 ; @ ^ |62| OR .L2X A6,B6,B6 ; |82| || [ B0] ADD .S2 1,B4,B4 ; @|64| || [ B0] ADDK .S1 32,A5 ; @|65| || [ B0] LDW .D1T1 *A2,A4 ; @ ^ |65| MV .L1X B6,A10 ; Define a twin register || MV .L2 B0,B2 ; @Inserted to split a long life || SUB .S1 A5,A3,A5 ; @|75| || LDW .D1T1 *++A2,A4 ; @@ ^ |62| ;** --------------------------------------------------------------------------* L5: ; PIPED LOOP EPILOG ADDK .S2 128,B9 ; |87| || [ B2] ZERO .L2 B6 ; || [ B2] ZERO .S1 A10 ; || SUB .L1X B7,1,A1 ; || [ B2] STW .D2T1 A10,*B5++ ; (E) @@|64| SUB .L2 B7,1,B7 ; || ADD .L1 A9,A5,A5 ; (E) @@|75| NEG .L1 A5,A3 ; (E) @@|77| MVC .S2 B8,CSR ; interrupts on || AND .L1 A8,A4,A6 ; (E) @@ ^ |74| || CMPLT .L2X A5,0,B1 ; (E) @@|75| ;** --------------------------------------------------------------------------* [ B1] ADD .L2 1,B4,B4 ; (E) @@|78| || [ B1] ADDK .S1 32,A5 ; (E) @@|79| || MV .S2 B1,B0 ; (E) @@Inserted to split a long life || OR .L1 A0,A6,A0 ; (E) @@|74| MV .L2 B4,B8 || MV .L1 A5,A11 || SHRU .S1 A0,A3,A7 ; (E) @@|77| || [ A1] B .S2 L1 ; |88| SHL .S1 A0,A5,A0 ; (E) @@|82| || [ B1] OR .L1 A7,A10,A10 ; (E) @@|77| [ B0] STW .D2T1 A10,*B5++ ; (E) @@|78| || [ B0] MV .L2X A10,B6 ; (E) @@Define a twin register MV .L1X B5,A12 || [ B0] ZERO .L2 B6 ; (E) @@|80| OR .L2X A0,B6,B6 ; (E) @@|82| MV .L1X B6,A10 ; (E) @@Define a twin register ; BRANCH OCCURS ; |88| ;** --------------------------------------------------------------------------* STW .D1T1 A10,*A12 ; |91| LDW .D2T1 *+SP(12),A11 ; |94| B .S2 B3 ; |94| || LDW .D2T1 *+SP(8),A10 ; |94| LDW .D2T1 *++SP(16),A12 ; |94| ADD .L1X 1,B8,A4 ; NOP 3 ; BRANCH OCCURS ; |94|