nbit	.set	B0
c1	.set	B1
c2	.set	B1
c3	.set	B2

src	.set	A3
dst	.set	B3

	.include	"otherRegisters"


	SHRU	x0, k, msb

	SUB	nbit, msb, c1:nbit

   [c1]	ADD	nbit, C32, nbit
||	AND	x0, mask, lsb

	SUB	nbit, k1, c2:nbit
||	SUB	k1, nbit, sr
||	OR	msk0, lsb, lsb
|| [c1]	STW	Ovalue, *dst++
|| [c1]	ZERO	Ovalue
||	LDW	*src++, x0

	SHRU	x0, k, msb
|| [c2]	ADD	nbit, C32, nbit
|| [c2]	SHRU	lsb, sr, Ov_out
||	MV	c2, c3

	SUB	nbit, msb, c1:nbit
||	SHL	lsb, nbit, lsb
|| [c2] OR	Ovalue, Ov_out, Ov_out
|| [c2]	ZERO	Ovalue

   [c1]	ADD	nbit, C32, nbit
||	AND	x0, mask, lsb
|| [c3]	STW	Ov_out, *dst++
||	OR	Ovalue, lsb, Ovalue