.global	_periph_init

_periph_init:	.cproc
	MVKL	0x01800000, A4	; EMIF base
	MVKH	0x01800000, A4
	MVKL	0xfff10221, A5	; Read Setup=1 Strobe=2 Hold=1
	MVKH	0xfff10221, A5
	STW	A5, *+A4[1]	; configuring EMIF CE1 space control

	MVKL	0x01880000, A4	; Expansion Bus Global Control (XBGC) register
	MVKH	0x01880000, A4
*	MVK	0x7000,	A5	; Clock = CPU/2
	MVK	0x6000,	A5	; Clock = CPU/4
*	MVK	0x5000, A5	; Clock = CPU/6
*	MVK	0x4000, A5	; Clock = CPU/8
	STW	A5, *A4

	;; ----------------------------------------
	;; McBSP1 Configuration for output FPHA
	;; ----------------------------------------
	MVKL	0x01900000, A4	; McBSP1 base address
	MVKH	0x01900000, A4
	MVKL	0x000100A0, A5
	MVKH	0x000100A0, A5
	STW	A5, *+A4[3]	; McBSP1 RCR (Receive control register)
	STW	A5, *+A4[4]	; McBSP1 XCR (Transmit control register)
	MVKL	0x20200008, A5
	MVKH	0x20200008, A5
	STW	A5, *+A4[5]	; McBSP1 SRGR (Sample rate generator register)
	MVK	0x00000A02, A5
	STW	A5, *+A4[9]	; McBSP1 PCR (Pin control register)
	MVKL	0x00C10001, A5
	MVKH	0x00C10001, A5
	STW	A5, *+A4[2]	; McBSP1 SPCR (Serial port control register)
	MVKL	0xdeadbeef, A5
	MVKH	0xdeadbeef, A5
	STW	A5, *+A4[1]	; Send a message to the serial port (DXR)

	;; ----------------------------------------
	;; McBSP2 Configuration for TTC input
	;; ----------------------------------------
	MVKL	0x01A40000, A4	; McBSP2 base address
	MVKH	0x01A40000, A4

	;; --------------------------------------------------
	;; McBSP0 PCR Configuration for general purpose I/O
	;; --------------------------------------------------
	;; DX0  is output
	;; FSX0 is output
	MVKL	0x018c0000, A4	; McBSP0 base address
	MVKH	0x018c0000, A4
	MVKL	0x00002800, A5	; XIOEN=1, FSXM=1, FSXP=0
	MVKH	0x00002800, A5	; XIOEN=1, FSXM=1, FSXP=0
	STW	A5, *+A4[9]	; McBSP1 PCR

	NOP
	NOP
	.return
	.endproc