;; This routine first test if INT10 was received. If yes,
	;; then the serial data is read and interpreted as follows:
	;; 0 -> dump energy histograms
	;; 1 -> dump time   histograms
	;; 2 -> power down.
	;; For DMA transfers, 4096 words from _ehist (or _thist) are sent
	;; to the histogram FIFO, using DMA channel 3. The transfer is split 
	;; into 16 frames of 256 words each, in order not to overflow the
	;; FPGA buffer. Frame synchronization is done via INT5.
	;; Before calling this routine for the first time, the DMA
	;; channel 3 destination address must be set to XCE2,
	;; and the word count in the Global Counter Reload B register
	;; must be set to 256.
	;; Modified 13 Apr 2001 by S.Simion
	;; Now splitting into 32 frames of 128 words each.

DMA_3		.set	0x01840044
DRR_0		.set	0x018c0000
		.global	_testSysCall
		.global	_ehist
		.global	_thist

_testSysCall:
		MVC	IFR, B0
||		MVKL	DRR_0, A3

		EXTU	B0, 21, 31, B0	; Test INT10
||		MVKH	DRR_0, A3

  [!B0]		B	B3		; No serial data => return
|| [B0]		LDW	*A3, B1		; Read serial data
||		MVKL	DMA_3, A3

		MVKH	DMA_3, A3
|| [B0]		MVK	0x400, B0	; To clear INT10 later
	
   [B0]		LDW	*A3, A1		; Read DMA primary control register

		MVKL	0x00180008, A4	; Set DMA secondary control register
||		MVKL	_ehist, B4	; Base address of energy histograms

		MVKH	0x00180008, A4
||		MVKH	_ehist, B4

; -- Serial data available
		CMPGT	B1, 1, A2	; Requests 0 and 1 are DMA requests
|| [B0]		MVC	B0, ICR		; Clearing INT10

; -- Return occurs
  [!A2]		B	B3		; Return from DMA request

; -- DMA primary control register available
  [!A2]		EXTU	A1, 28, 30, A2	; Check if DMA channel is busy
|| [B1]		MVKL	_thist, B4	; Base address of time histograms

  [!A2]		STW	A4, *+A3[2]	; Load secondary control register
|| [B1]		MVKH	_thist, B4
||		MVK	128, A5		; Word count

  [!A2]		STW	B4,*+A3[4]	; Load source address
||		MVKL	0x04015011, B5
||		MVKLH	32, A5		; Frame count

  [!A2]		STW	A5,*+A3[8]	; Load frame count and word count
||		MVKH	0x04015011, B5

  [!A2]		STW	B5, *A3		; Trigger the transfer

; -- Return occurs
		MVK	0x7000, B4	; Power-down PD3
		MVC	B4, CSR
		IDLE