;; This routine first test if INT7 was received. If yes,
	;; then 4096 words from _ehist (or _thist) are sent to
	;; the histogram FIFO, using DMA channel 3. The transfer
	;; is split into 16 frames of 256 words each, in order
	;; not to overflow the FPGA buffer. Frame synchronization
	;; is done via INT5.
	;; Before calling this routine for the first time, the DMA
	;; channel 3 destination address must be set to XCE2,
	;; and the word count in the Global Counter Reload B register
	;; must be set to 256.

DMA_3		.set	0x01840044

		.global	_testDumpHisto
		.global	_ehist
		.global	_thist

_testDumpHisto:
		MVC	IFR, B0
||		MVKL	DMA_3, A3

		EXTU	B0, 24, 31, B0	; Test INT7
||		MVKH	DMA_3, A3

   [!B0]	B	B3		; No request
|| [B0]		LDW	*A3, A1

		MVKL	0x00180008, A4	; Secondary control register
||		MVKL	_ehist, B4	; Source address

		MVKH	0x00180008, A4	; FSIG=1, RSPOL=1
||		MVKH	_ehist, B4	; Source address

   [B0]		MVK	0x80, B0	; To clear INT7 later

   [B0]		B	B3		; Final return

; -- By now A1 is loaded
		EXTU	A1, 28, 30, A1	; check if DMA3 available

; -- Branch occurs 
   [!A1]	STW	A4,*+A3[2]	; Secondary control register
|| [!A1]	MVK	256, A5		; Word count

   [!A1]	STW	B4,*+A3[4]	; Load source address
|| [!A1]	MVKL	0x04015011, B5	; Primary control register
|| [!A1]	MVKLH	16, A5		; Frame count

   [!A1]	STW	A5,*+A3[8]	; Load frame count and word count
|| [!A1]	MVKH	0x04015011, B5	; FS=1, RSYNC=5, DST DIR=0, CNT RLD B

   [!A1]	STW	B5, *A3		; Trigger the transfer
|| [!A1]	MVC	B0, ICR		; Clearing INT7
; -- Return occurs